仿真引导的布尔重替换
Simulation-Guided Boolean Resubstitution
摘要：
本文提出了一种新的基于电路仿真的逻辑优化范式，它减少了对布尔计算的需求，如SAT求解或构造BDD。本文开发了一个布尔重替换框架，以证明所提出的方法的有效性。方法来生成高表达的模拟模式的开发，和所生成的模式被用于在resubstitution潜在的resubstitution候选人的有效过滤，以减少SAT验证的需要。实验结果表明，在电路尺寸减小的改进实现了高达74%，相比一个国家的最先进的重新替换算法。
英文摘要：
This paper proposes a new logic optimization paradigm based on circuit simulation, which reduces the need for Boolean computations such as SAT-solving or constructing BDDs. The paper develops a Boolean resubstitution framework to demonstrate the effectiveness of the proposed approach. Methods to generate highly expressive simulation patterns are developed, and the generated patterns are used in resubstitution for efficient filtering of potential resubstitution candidates to reduce the need for SAT validation. Experimental results show that improvements in circuit size reduction were achieved by up to 74%, compared to a state-of-the-art resubstitution algorithm.
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