深入了解基于势阱的纳米级FDSOI MOSFET使用掺杂硅管-基于模拟和器件物理的研究：第一部分：理论和方法
Insight into Potential Well Based Nanoscale FDSOI MOSFET Using Doped Silicon Tubs- A Simulation and Device Physics Based Study: Part I: Theory and Methodology
摘要：
报道了一种在栅长为20 nm的FDSOI MOSFET的源极和漏极下具有掺杂硅区（槽）的新型平面器件。掺杂的硅区域导致在FDSOI MOSFET的源极和漏极区域中形成势阱（PW），因此，该器件被称为基于势阱的FDSOI MOSFET（PWFDSOI MOSFET）。对PWFDSOI MOSFET的模拟和器件物理研究表明，器件的关断电流降低了几个数量级。在20 nm栅长的PWFDSOI MOSFET中获得了22 pA/um的低IOF、1.5 × 107的高ION /IOF比和76 mV/decade的亚阈值摆幅。该研究是在具有无应变硅沟道的器件上进行的。
英文摘要：
A novel planar device having doped silicon regions (tubs) under the source and drain of an FDSOI MOSFET is reported at 20 nm gate length. The doped silicon regions result in formation of potential wells (PW) in the source and drain regions of FDSOI MOSFET and thus, the device being called as Potential Well Based FDSOI MOSFET (PWFDSOI MOSFET). Simulation and device physics study on PWFDSOI MOSFET showed reduction in the OFF current of the device by orders of magnitude. A low IOF F of 22 pA/um, high ION /IOF F ratio of 1.5 x 107 and subthreshold swing of 76 mV/decade were achieved in 20 nm gate length PWFDSOI MOSFET. The study was performed on devices with unstrained silicon channel.
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