CNN中卷积和解卷积的统一硬件架构
A Unified Hardware Architecture for Convolutions and Deconvolutions in CNN
摘要：
本文提出了一种用于图像分割的可扩展神经网络硬件结构。通过共享相同的计算资源，卷积和去卷积操作都由相同的处理元件阵列处理。此外，对片上和片外存储器的访问进行了优化，以减轻部分和所带来的负担。以SegNet-Basic为例，在Xilinx ZC 706 FPGA上实现，卷积和反卷积的性能分别达到151.5 GOPS和94.3 GOPS。这种统一的卷积/去卷积设计适用于其他具有去卷积的CNN。
英文摘要：
In this paper, a scalable neural network hardware architecture for image segmentation is proposed. By sharing the same computing resources, both convolution and deconvolution operations are handled by the same process element array. In addition, access to on-chip and off-chip memories is optimized to alleviate the burden introduced by partial sum. As an example, SegNet-Basic has been implemented using the proposed unified architecture by targeting on Xilinx ZC706 FPGA, which achieves the performance of 151.5 GOPS and 94.3 GOPS for convolution and deconvolution respectively. This unified convolution/deconvolution design is applicable to other CNNs with deconvolution.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
