电路逆向工程错误下基于可满足性的攻击有效性
Efficacy of Satisfiability Based Attacks in the Presence of Circuit Reverse Engineering Errors
摘要：
知识产权（IP）盗窃是集成电路（IC）行业的一个严重问题。为了解决这个问题，逻辑锁定对策将逻辑电路转换为不同的逻辑电路以混淆其内部细节。由混淆引起的变换仅在应用编程的秘密密钥时被反转，从而保持电路的原始功能。这种技术容易受到基于可满足性（SAT）的攻击。但是为了成功，基于SAT的攻击隐含地假设完美的逆向工程电路，这在实践中很难实现，这是由于自动电路提取引起的逆向工程（RE）错误。在本文中，我们分析了随机电路RE错误对基于SAT的攻击成功的影响。对ISCAS、MCNC基准测试以及成熟的RISC-V CPU的实证评估表明，攻击成功率随着随机RE错误数量的增加而呈指数级下降。因此，对手要么必须配备接近完美的RE工具，要么提出更好的基于SAT的攻击，可以与RE缺陷一起工作。
英文摘要：
Intellectual Property (IP) theft is a serious concern for the integrated circuit (IC) industry. To address this concern, logic locking countermeasure transforms a logic circuit to a different one to obfuscate its inner details. The transformation caused by obfuscation is reversed only upon application of the programmed secret key, thus preserving the circuit's original function. This technique is known to be vulnerable to Satisfiability (SAT)-based attacks. But in order to succeed, SAT-based attacks implicitly assume a perfectly reverse-engineered circuit, which is difficult to achieve in practice due to reverse engineering (RE) errors caused by automated circuit extraction. In this paper, we analyze the effects of random circuit RE-errors on the success of SAT-based attacks. Empirical evaluation on ISCAS, MCNC benchmarks as well as a fully-fledged RISC-V CPU reveals that the attack success degrades exponentially with increase in the number of random RE-errors. Therefore, the adversaries either have to equip RE-tools with near perfection or propose better SAT-based attacks that can work with RE-imperfections.
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