堆叠您的芯片：押注3D集成以增强摩尔定律缩放
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling
摘要：
3D集成，即，使用并行或顺序处理的集成电路层的堆叠随着摩尔定律缩放的减缓而获得快速的工业采用。3D堆叠有望在性能、功耗和成本方面获得潜在收益，但实际收益幅度取决于最终应用、技术选择和设计。在这次演讲中，我们将讨论与3D设计相关的一些关键挑战，以及3D设计如何要求我们打破微架构，电路/物理设计和制造技术的传统孤岛，以实现3D技术所承诺的收益。
英文摘要：
3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moore's law scaling. 3D stacking promises potential gains in performance, power and cost but the actual magnitude of gains varies depending on end-application, technology choices and design. In this talk, we will discuss some key challenges associated with 3D design and how design-for-3D will require us to break traditional silos of micro-architecture, circuit/physical design and manufacturing technology to work across abstractions to enable the gains promised by 3D technologies.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
