Good process-to-compute-node mappings can be decisive for well performing HPC applications. A special, important class of process-to-node mapping problems is the problem of mapping processes that communicate in a sparse stencil pattern to Cartesian grids. By thoroughly exploiting the inherently present structure in this type of problem, we devise three novel distributed algorithms that are able to handle arbitrary stencil communication patterns effectively. We analyze the expected performance of our algorithms based on an abstract model of inter- and intra-node communication. An extensive experimental evaluation on several HPC machines shows that our algorithms are up to two orders of magnitude faster in running time than a (sequential) high-quality general graph mapping tool, while obtaining similar results in communication performance. Furthermore, our algorithms also achieve significantly better mapping quality compared to previous state-of-the-art Cartesian grid mapping algorithms. This results in up to a threefold performance improvement of an MPI_Neighbor_alltoall exchange operation. Our new algorithms can be used to implement the MPI_Cart_create functionality.
Fast Stencil-Code Computation on a Wafer-Scale Processor
基于CPU和基于GPU的系统的性能通常对于PDE码是低的，其中必须求解大型、稀疏且通常结构化的线性方程组。迭代求解器受到数据移动的限制，包括缓存和内存之间以及节点之间。在这里，我们描述的解决方案，这样的系统的方程的Cerebras系统CS-1，晶圆级处理器，具有内存带宽和通信延迟执行良好。我们实现了0.86 PFLOPS在一个单一的晶圆级系统的解决方案，由BiCGStab的线性系统所产生的7点有限差分模板上600 X 595 X 1536网格，实现约三分之一的机器的峰值性能。我们解释了系统，它的体系结构和编程，以及它在这个问题和相关问题上的表现。我们讨论内存容量和浮点精度的问题。我们概述了将这项工作扩展到全面应用的计划。
An MLIR Lowering Pipeline for Stencils at Wafer-Scale
Technische Universität Berlin（柏林工业大学）；EPCC（爱丁堡计算中心）；School of Informatics, The University of Edinburgh（爱丁堡大学信息学院）；The University of Edinburgh（爱丁堡大学）；Imperial College London（伦敦帝国理工学院）；University of Cambridge（剑桥大学）
