多层感知器（MLP）在降压FPGA BRAM操作下的功率和精度
Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation
摘要：
在本文中，我们利用现场可编程门阵列（FPGA）的块RAM（BRAM）的积极电源电压降阶技术，以提高多层感知器（MLP）的能源效率。此外，我们还评估和改进了这种加速器的弹性。通过在几个代表性FPGA结构上的实验，我们观察到，直到最小安全电压电平，即，Vmin时，MLP精度不受影响。该安全区域涉及大的电压保护带。此外，它涉及一个较窄的电压区域，其中由于电路延迟的增加，故障开始出现在存储器中，但这些故障被MLP掩盖，因此，其精度不受影响。然而，由于快速增加的高故障率，进一步的欠转会导致显著的精度损失。基于这些欠转故障的特征，我们提出了故障缓解技术，可以有效地提高这种加速器的弹性行为。我们的评估是基于四个FPGA平台。平均而言，我们实现了90%以上的节能，精度损失可忽略不计，最高为0.1%。
英文摘要：
In this paper, we exploit the aggressive supply voltage underscaling technique in Block RAMs (BRAMs) of Field Programmable Gate Arrays (FPGAs) to improve the energy efficiency of Multi-Layer Perceptrons (MLPs). Additionally, we evaluate and improve the resilience of this accelerator. Through experiments on several representative FPGA fabrics, we observe that until a minimum safe voltage level, i.e., Vmin the MLP accuracy is not affected. This safe region involves a large voltage guardband. Also, it involves a narrower voltage region where faults start to appear in memories due to the increased circuit delay, but these faults are masked by MLP, and thus, its accuracy is not affected. However, further undervolting causes significant accuracy loss as a result of the fast-increasing high fault rates. Based on the characterization of these undervolting faults, we propose fault mitigation techniques that can effectively improve the resilience behavior of such accelerator. Our evaluation is based on four FPGA platforms. On average, we achieve >90% energy saving with a negligible accuracy loss of up to 0.1%.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
