LiteX：基于Migen Python的开源SoC构建器和库DSL
LiteX: an open-source SoC builder and library based on Migen Python DSL
摘要：
LiteX是GitHub托管的SoC构建器/ IP库和实用程序，可用于创建SoC和完整的FPGA设计。除了开源和BSD许可外，它的独创性还在于它的IP组件完全使用Migen Python内部DSL描述，这简化了它的设计。LiteX已经支持各种软核CPU和基本外设，不依赖于专有IP块或生成器。本文概述了LiteX：给出了两个基于FPGA的真实SoC设计。它们都在设计入口、库和集成功能方面利用了LiteX方法。第一个基于RISC-V内核，第二个基于LM 32内核。在第二个用例中，我们进一步展示了与LiteX相结合的完全开源工具链的使用。
英文摘要：
LiteX is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various softcores CPUs and essential peripherals, with no dependencies on proprietary IP blocks or generators. This paper provides an overview of LiteX: two real SoC designs on FPGA are presented. They both leverage the LiteX approach in terms of design entry, libraries and integration capabilities. The first one is based on RISC-V core, while the second is based on a LM32 core. In the second use case, we further demonstrate the use of a fully open-source toolchain coupled with LiteX.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
