arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2005.01386cs.LGcs.AReess.SPmath.OC
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PowerPlanningDL:基于深度学习的片上电网设计可靠性感知框架

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning

IIT Guwahati(印度理工学院古瓦哈提分校)

Sukanta Dey, Sukumar Nandi, Gaurav Trivedi

摘要:

随着芯片设计复杂度的增加,超大规模集成电路的物理设计已经成为一项耗时的任务,这是一个迭代的设计过程。电源规划是VLSI物理设计中布局规划的一部分,其中设计电源网格网络以便为所有底层功能块提供足够的电源。电力规划还需要多个迭代步骤来创建电网网络,同时满足允许的最坏情况IR降和电迁移(EM)裕度。本文首次引入了基于深度学习(DL)的框架来近似预测电网网络的初始设计,考虑不同的可靠性约束。所提出的框架减少了许多迭代设计步骤,加快了总的设计周期。采用基于神经网络的多目标回归技术建立DL模型。完成特征提取,并且从IBM处理器中提取的一些电网设计的平面图生成训练数据集。使用生成的数据集训练DL模型。所提出的基于DL的框架使用一组新的电网规范(通过扰动训练阶段使用的设计获得)进行验证。结果表明,预测的电网设计更接近于原始设计,预测误差最小(~2%)。所提出的基于DL的方法还提高了设计周期时间,对于标准电网基准测试,加速比为~ 6倍。

英文摘要:

With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the first time, this paper introduces Deep learning (DL)-based framework to approximately predict the initial design of the power grid network, considering different reliability constraints. The proposed framework reduces many iterative design steps and speeds up the total design cycle. Neural Network-based multi-target regression technique is used to create the DL model. Feature extraction is done, and the training dataset is generated from the floorplans of some of the power grid designs extracted from the IBM processor. The DL model is trained using the generated dataset. The proposed DL-based framework is validated using a new set of power grid specifications (obtained by perturbing the designs used in the training phase). The results show that the predicted power grid design is closer to the original design with minimal prediction error (~2%). The proposed DL-based approach also improves the design cycle time with a speedup of ~6X for standard power grid benchmarks.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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