1200万个Hodgkin-Huxley神经元网络在单芯片上的实现
Implementation of a 12-Million Hodgkin-Huxley Neuron Network on a Single Chip
摘要：
了解人类大脑是21世纪科学家面临的最大挑战。Hodgkin-Huxley（HH）模型是最成功的脑生物逼真模拟的数学模型之一。然而，HH神经元的模拟涉及复杂的计算，这使得大规模脑网络的实现变得困难。在本文中，我们提出了一种硬件架构，有效地计算一个大规模的HH神经元网络。该结构基于神经元机器的硬件结构，由于其只有一个计算节点，因此具有速度的限制。所提出的架构本质上是一个非冯诺依曼同步系统与多个计算节点，称为硬件神经元，以实现线性加速比。在本文中，设计的数字电路，计算大规模的HH神经元网络作为一个例子，提供了一个详细的说明所提出的架构。该设计支持尖峰和短期和长期可塑性突触的轴突传导延迟，以及浮点精度HH神经元。该设计在现场可编程门阵列（FPGA）芯片上实现，并实时的计算一百万个HH神经元的网络。所实现的系统可以计算具有多达1200万个HH神经元和6亿个突触的网络。所提出的设计方法可以促进支持复杂神经元模型的系统的设计及其在可重构FPGA芯片上的灵活实现。
英文摘要：
Understanding the human brain is the biggest challenge for scientists in the twenty-first century. The Hodgkin-Huxley (HH) model is one of the most successful mathematical models for bio-realistic simulations of the brain. However, the simulation of HH neurons involves complex computation, which makes the implementation of large-scale brain networks difficult. In this paper, we propose a hardware architecture that efficiently computes a large-scale network of HH neurons. This architecture is based on the neuron machine hardware architecture, which has the limitation of speed as it has only one computation node. The proposed architecture is essentially a non-Von Neumann synchronous system with multiple computation nodes, called hardware neurons, to achieve linear speedup. In this paper, the design of a digital circuit that computes large-scale networks of HH neurons is presented as an example to provide a detailed description of the proposed architecture. This design supports axonal conduction delay of spikes and short- and long-term plasticity synapses, along with floating-point precision HH neurons. The design is implemented on a field-programmable gate array (FPGA) chip and computes a network of one million HH neurons in near real time. The implemented system can compute a network with up to 12 million HH neurons and 600 million synapses. The proposed design method can facilitate the design of systems supporting complex neuron models and their flexible implementation on reconfigurable FPGA chips.
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