ApproxFPGAs：为基于FPGA的系统提供基于ASIC的近似算术组件
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems
摘要：
针对ASIC的近似电路（Approximate Circuits，AC）的发展，已经有了大量的研究。然而，以前的研究表明，基于ASIC的AC在基于FPGA的加速器中提供不对称的增益。因此，对于ASIC来说可能是帕累托最优的AC对于FPGA来说可能不是帕累托最优的。在这项工作中，我们提出了ApproxFPGA的方法，使用机器学习模型，以减少探索时间分析国家的最先进的ASIC为基础的AC，以确定一组帕累托最优的FPGA为基础的AC。我们还进行了一个案例研究，以说明通过在最先进的自动化框架中部署这些基于FPGA的帕累托最优AC来系统地生成帕累托最优近似加速器所获得的好处，这些加速器可以部署在基于FPGA的系统中以实现高性能或低功耗。
英文摘要：
There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
