高效、任意高精度的线性代数硬件对数运算
Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
摘要：
对数系统（LNS）可以说是不广泛使用，由于指数电路开销求和表相对于算术精度。已经提出了减少这种开销的方法，但仍然产生具有高芯片面积和功率要求的设计。使用仍然限于较低精度或高乘/加比的情况，而大部分线性代数（接近1：1乘/加比）不符合条件。我们提出了一个双基地的近似对数运算的浮点使用，但不像LNS很容易完全流水线，可扩展到任意精度与$O(n^2)$开销，和能源效率在1：1的乘/加比。与浮点32或浮点64矢量内积和FMA相比，我们的设计在7 nm CMOS中的能量效率分别提高了2.3倍和4.6倍。它取决于exp和log评估，能效提高5.4倍和3.2倍，芯片面积增加0.23倍和0.37倍，与标准双曲线CORDIC相比，使用移位相加和近似ODE积分，以Revol和Yaksohn的风格获得相同的精度。该技术是计算机视觉、图形和机器学习应用中低功耗、高精度强化线性代数的一种新型设计替代方案。
英文摘要：
The logarithmic number system (LNS) is arguably not broadly used due to exponential circuit overheads for summation tables relative to arithmetic precision. Methods to reduce this overhead have been proposed, yet still yield designs with high chip area and power requirements. Use remains limited to lower precision or high multiply/add ratio cases, while much of linear algebra (near 1:1 multiply/add ratio) does not qualify. We present a dual-base approximate logarithmic arithmetic comparable to floating point in use, yet unlike LNS it is easily fully pipelined, extendable to arbitrary precision with $O(n^2)$ overhead, and energy efficient at a 1:1 multiply/add ratio. Compared to float32 or float64 vector inner product with FMA, our design is respectively 2.3x and 4.6x more energy efficient in 7 nm CMOS. It depends on exp and log evaluation 5.4x and 3.2x more energy efficient, at 0.23x and 0.37x the chip area for equivalent accuracy versus standard hyperbolic CORDIC using shift-and-add and approximated ODE integration in the style of Revol and Yakoubsohn. This technique is a novel design alternative for low power, high precision hardened linear algebra in computer vision, graphics and machine learning applications.
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