光学使能、光谱切片ADC中的锁模激光时序抖动限制
Mode-locked laser timing jitter limitation in optically enabled, spectrally sliced ADCs
摘要：
新型模数转换器（ADC）架构的出现是为了满足不断提高的采样速率和有效位数（ENOB）的需求。纯电气ADC中的ENOB主要限制在于振荡器的抖动相对较高，对于最先进的器件，抖动约为几十fs。与同类最佳的钛宝石锁模激光器（MLL）在阿秒范围内获得的极低抖动相比，混合电光架构显然可以显著提高转换器的有效位数（ENOB）。在讨论了系统架构和实现细节后，我们对光学使能的光谱切片ADC中光源引起的有效位数限制进行了建模和分析。用于电光信号转换的光载波的相位噪声不传播到重建的数字化信号，因此不代表基本限制。用于为各个切片生成参考音调的MLL的光学相位噪声也不会从根本上影响转换后的信号，只要它在所有梳状线之间保持相关即可。另一方面，MLL的定时抖动（也反映在其RF线宽中）从根本上限制了ADC性能，因为它直接映射为转换信号的抖动。光子使能、频谱切片ADC的混合特性意味着利用多个带宽降低的电ADC来转换并行切片，从而导致抖动从为其提供时钟的电振荡器传播。由于电ADC的采样率降低，与整个系统相比，所提出的架构的整体噪声性能相对于全电ADC得到了显著改善。
英文摘要：
Novel analog-to-digital converter (ADC) architectures are motivated by the demand for rising sampling rates and effective number of bits (ENOB). The main limitation on ENOB in purely electrical ADCs lies in the relatively high jitter of oscillators, in the order of a few tens of fs for state-of-the-art components. When compared to the extremely low jitter obtained with best-in-class Ti:sapphire mode-locked lasers (MLL), in the attosecond range, it is apparent that a mixed electrical-optical architecture could significantly improve the converters' ENOB. We model and analyze the ENOB limitations arising from optical sources in optically enabled, spectrally sliced ADCs, after discussing the system architecture and implementation details. The phase noise of the optical carrier, serving for electro-optic signal transduction, is shown not to propagate to the reconstructed digitized signal and therefore not to represent a fundamental limit. The optical phase noise of the MLL used to generate reference tones for individual slices also does not fundamentally impact the converted signal, so long as it remains correlated among all the comb lines. On the other hand, the timing jitter of the MLL, as also reflected in its RF linewidth, is fundamentally limiting the ADC performance, since it is directly mapped as jitter to the converted signal. The hybrid nature of a photonically enabled, spectrally sliced ADC implies the utilization of a number of reduced bandwidth electrical ADCs to convert parallel slices, resulting in the propagation of jitter from the electrical oscillator supplying their clock. Due to the reduced sampling rate of the electrical ADCs, as compared to the overall system, the overall noise performance of the presented architecture is substantially improved with respect to a fully electrical ADC.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
