DNN辅助的有限块长MLC闪存读电压阈值优化
DNN-aided Read-voltage Threshold Optimization for MLC Flash Memory with Finite Block Length
摘要:
多级单元(MLC)NAND闪存的纠错性能与纠错码(ECC)的块长度和读电压阈值的对数似然比(LLR)密切相关。针对这一问题,本文对MLC闪存的读电压阈值进行了优化,以提高有限块长ECC的译码性能。首先,通过对有限块长度下的信道编码率(CCR)和译码错误概率的分析,建立了以最大译码错误概率最小为目标的读电压阈值优化问题。其次,我们提出了一种交叉迭代搜索(CIS)算法来优化读电压阈值下的闪存通道的完美知识。然而,由于实际上闪存的数据保持时间(DRT)很难记录,因此分析表征数据保持噪声(DRN)影响下的电压分布具有挑战性。为了解决这个问题,我们开发了一种深度神经网络(DNN)辅助优化策略来优化读取电压阈值,其中采用多层感知(MLP)网络来学习电压分布和读取电压阈值之间的关系。仿真结果表明,与现有方案相比,所提出的DNN辅助的读电压阈值优化策略结合设计良好的LDPC码,不仅可以提高编程擦除(PE)耐受性,而且可以降低读延迟。
英文摘要:
The error correcting performance of multi-level-cell (MLC) NAND flash memory is closely related to the block length of error correcting codes (ECCs) and log-likelihood-ratios (LLRs) of the read-voltage thresholds. Driven by this issue, this paper optimizes the read-voltage thresholds for MLC flash memory to improve the decoding performance of ECCs with finite block length. First, through the analysis of channel coding rate (CCR) and decoding error probability under finite block length, we formulate the optimization problem of read-voltage thresholds to minimize the maximum decoding error probability. Second, we develop a cross iterative search (CIS) algorithm to optimize read-voltage thresholds under the perfect knowledge of flash memory channel. However, it is challenging to analytically characterize the voltage distribution under the effect of data retention noise (DRN), since the data retention time (DRT) is hard to be recorded for flash memory in reality. To address this problem, we develop a deep neural network (DNN) aided optimization strategy to optimize the read-voltage thresholds, where a multi-layer perception (MLP) network is employed to learn the relationship between voltage distribution and read-voltage thresholds. Simulation results show that, compared with the existing schemes, the proposed DNN-aided read-voltage threshold optimization strategy with a well-designed LDPC code can not only improve the program-and-erase (PE) endurance but also reduce the read latency.
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