基于蜘蛛巢恒等式的快速高效T计数缩减技术
Fast and effective techniques for T-count reduction via spider nest identities
AI总结：
针对容错量子计算中T门资源成本高的问题，提出基于蜘蛛巢恒等式的T计数缩减技术，可快速有效降低多个量子电路的T计数。
摘要：
在容错量子计算系统中，实现（近似）通用量子计算通常以实现Clifford+T操作来描述，即由CNOT门、阿达马门和π/2相位旋转构成的电路，再加上T操作（π/4相位旋转）。对于许多纠错码而言，Clifford操作的容错实现所需资源远低于T门，这促使人们寻找实现相同变换的方法，使涉及的T计数（即所用T门的数量）尽可能低。针对该问题的研究[arXiv:1206.0758, 1303.2042, 1308.4134, 1601.07363, 1606.01904, 1701.00140]已发现，该问题与NP难的张量分解问题[arXiv:1712.01557]密切相关，且等同于解码指数长度Reed-Muller码的难题[arXiv:1601.07363]。因此该问题在实践中只能采用近似优化，即开发一系列策略并通过务实的方案加以运用。沿着这一思路，我们提出了基于“蜘蛛巢恒等式”有效应用的T计数缩减技术：蜘蛛巢恒等式是易于识别的奇偶相位操作乘积，其效果等价于恒等操作。我们通过在多个电路的T计数上取得优化验证了这些技术的有效性，其运行时间通常不到泡一杯新咖啡的时间。
英文摘要：
In fault-tolerant quantum computing systems, realising (approximately) universal quantum computation is usually described in terms of realising Clifford+T operations, which is to say a circuit of CNOT, Hadamard, and $π/2$-phase rotations, together with T operations ($π/4$-phase rotations). For many error correcting codes, fault-tolerant realisations of Clifford operations are significantly less resource-intensive than those of T gates, which motivates finding ways to realise the same transformation involving T-count (the number of T gates involved) which is as low as possible. Investigations into this problem [arXiv:1206.0758, 1303.2042, 1308.4134, 1601.07363, 1606.01904, 1701.00140] has led to observations that this problem is closely related to NP-hard tensor decomposition problems [arXiv:1712.01557] and is tantamount to the difficult problem of decoding exponentially long Reed-Muller codes [arXiv:1601.07363]. This problem then presents itself as one for which must be content in practise with approximate optimisation, in which one develops an array of tactics to be deployed through some pragmatic strategy. In this vein, we describe techniques to reduce the T-count, based on the effective application of "spider nest identities": easily recognised products of parity-phase operations which are equivalent to the identity operation. We demonstrate the effectiveness of such techniques by obtaining improvements in the T-counts of a number of circuits, in run-times which are typically less than the time required to make a fresh cup of coffee.
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