LLHD：硬件描述语言的多级中间表示
LLHD: A Multi-level Intermediate Representation for Hardware Description Languages
摘要：
现代硬件描述语言（HDL），如SystemVerilog或VHDL，由于其纯粹的复杂性，不足以通过现代电路设计流程传输设计。相反，每个设计自动化工具都将HDL降低到自己的中间表示（IR）。这些工具是单片的，并且大多是专有的，在HDL的实现方面存在分歧，并且虽然存在许多冗余IR，但今天没有IR可以用于整个电路设计流程。为了解决这个问题，我们提出了LLHD多电平IR。LLHD被设计为简单，明确的数字电路的参考描述，但完全捕获现有的HDL。我们用参考编译器在像完整CPU内核那样复杂的设计上展示了这一点。LLHD降低了接近硬件的结构IR的通行证，很容易与现有的工具集成。LLHD为HDL和工具的创新奠定了基础，而无需冗余编译器或不相交的IR。例如，我们实现了一个LLHD模拟器，其运行速度比商业模拟器快2.4倍，但产生等效的周期准确的结果。一个初始的垂直集成的研究原型是能够代表所有级别的IR，实现降低从行为到结构IR，并涵盖了足够的子集SystemVerilog支持一个完整的CPU设计。
英文摘要：
Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermediate Representation (IR). These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow. To solve this problem, we propose the LLHD multi-level IR. LLHD is designed as simple, unambiguous reference description of a digital circuit, yet fully captures existing HDLs. We show this with our reference compiler on designs as complex as full CPU cores. LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools. LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs. For instance, we implement an LLHD simulator that runs up to 2.4x faster than commercial simulators but produces equivalent, cycle-accurate results. An initial vertically-integrated research prototype is capable of representing all levels of the IR, implements lowering from the behavioural to the structural IR, and covers a sufficient subset of SystemVerilog to support a full CPU design.
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