SoftWear：非易失性主存储器的纯软件内存内损耗均衡
SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory
摘要：
在过去几年中，字节可寻址非易失性存储器（NVM）的几种新兴技术已经被认为取代DRAM作为计算机系统中的主存储器。与DRAM相比，NVM技术如相变存储器（PCM）或铁电RAM（FeRAM）的写耐久性较低的缺点已经在文献中得到解决。作为一种解决方案，已经提出了存储器内损耗均衡技术，其旨在平衡所有存储单元上的损耗水平以实现增加的存储器寿命。通常，为了应用文献中提出的这种先进的老化感知损耗均衡技术，将额外的特殊硬件引入存储器系统中以提供关于单元年龄的必要信息，从而实现老化感知损耗均衡决策。本文提出了基于普通CPU特性的纯软件老化感知耗损均衡，并且不依赖于来自存储器子系统的任何额外硬件支持。具体来说，我们利用存储管理单元（MMU），性能计数器，和中断近似的内存写入计数作为老化指标。虽然纯软件方法可能会导致稍微差一点的损耗均衡，但它适用于常见的硬件。我们通过统计采样近似当前单元年龄并通过MMU执行物理内存重映射来实现页面级粗粒度磨损均衡。这种方法会导致内存页内的内存使用模式不一致。因此，我们进一步提出了一个细粒度的磨损平衡在C / C++编译软件的堆栈区域。通过应用这两种损耗均衡技术，我们实现了理想存储器寿命的最高$78.43\%$，与没有任何损耗均衡的寿命相比，这是超过$900$的一个因子的寿命改进。
英文摘要：
Several emerging technologies for byte-addressable non-volatile memory (NVM) have been considered to replace DRAM as the main memory in computer systems during the last years. The disadvantage of a lower write endurance, compared to DRAM, of NVM technologies like Phase-Change Memory (PCM) or Ferroelectric RAM (FeRAM) has been addressed in the literature. As a solution, in-memory wear-leveling techniques have been proposed, which aim to balance the wear-level over all memory cells to achieve an increased memory lifetime. Generally, to apply such advanced aging-aware wear-leveling techniques proposed in the literature, additional special hardware is introduced into the memory system to provide the necessary information about the cell age and thus enable aging-aware wear-leveling decisions. This paper proposes software-only aging-aware wear-leveling based on common CPU features and does not rely on any additional hardware support from the memory subsystem. Specifically, we exploit the memory management unit (MMU), performance counters, and interrupts to approximate the memory write counts as an aging indicator. Although the software-only approach may lead to slightly worse wear-leveling, it is applicable on commonly available hardware. We achieve page-level coarse-grained wear-leveling by approximating the current cell age through statistical sampling and performing physical memory remapping through the MMU. This method results in non-uniform memory usage patterns within a memory page. Hence, we further propose a fine-grained wear-leveling in the stack region of C / C++ compiled software. By applying both wear-leveling techniques, we achieve up to $78.43\%$ of the ideal memory lifetime, which is a lifetime improvement of more than a factor of $900$ compared to the lifetime without any wear-leveling.
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