Fakernet --基于FPGA的小型快速TCP和UDP通信
Fakernet -- small and fast FPGA-based TCP and UDP communication
摘要：
数据采集系统的一个共同主题是将数据从数字化前端模块传输到稳定的存储和在线分析。如今，一个不错的选择是将其建立在无处不在、商业化和廉价的以太网技术基础上。提出了一种固件构建块，该固件构建块使用数据流架构将前端电子设备的FPGA变成TCP数据源和UDP控制接口。总体性能目标是能够使1 Gbps网络链路饱和，同时使用很少的FPGA资源。目标是用普通以太网设备取代定制数据总线和协议的使用。这些目标是通过刚刚足够的一致性来实现的，使得在与这里提出的Fakernet系统接口的PC设备中不需要特殊的驱动器。一个重要的设计选择是在内部将所有数据包数据作为16位字处理，从而降低时钟速度要求。有利的情况是，即使在1Gbps的速度下，对于本地网段，往返时间通常远低于500微秒。因此，不超过50 kiB的未确认数据需要在传输中，允许在没有TCP窗口缩放的情况下使网络链路饱和。到目前为止，Fakernet系统已被证明在11.7 MB/s的TCP输出数据下使100 Mbps链路饱和，并且能够以超过450 kword/s的速度进行32位控制寄存器访问。
英文摘要：
A common theme of data acquisition systems is the transport of data from digitising front-end modules to stable storage and online analysis. A good choice today is to base this on the ubiquitous, commercially and cheaply available Ethernet technology. A firmware building block to turn already the FPGA of front-end electronics into a TCP data source and UDP control interface using a data-flow architecture is presented. The overall performance targets are to be able to saturate a 1 Gbps network link with outbound data, while using few FPGA resources. The goal is to replace the use of custom data buses and protocols with ordinary Ethernet equipment. These objectives are achieved by being just-enough conforming, such that no special drivers are needed in the PC equipment interfacing with the here presented Fakernet system. An important design choice is to handle all packet-data internally as 16-bit words, thus reducing the clock-speed requirements. An advantageous circumstance is that even at 1 Gbps speeds, for local network segments, the round-trip times are usually well below 500 microseconds. Thus, less than 50 kiB of unacknowledged data needs to be in-flight, allowing to saturate a network link without TCP window scaling. The Fakernet system has so far been shown to saturate a 100 Mbps link at 11.7 MB/s of TCP output data, and able to do 32-bit control register accesses at over 450 kword/s.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
