软件无线电的软硬件协同设计：IEEE 802.11 p接收机案例研究
Hardware-Software Codesign for Software Defined Radio: IEEE 802.11p receiver case study
摘要：
软件定义无线电（SDR）平台是设计新无线技术或改进现有技术规范的有用工具。IEEE 802.11p是无线车载自组织网络（Wireless Vehicular Ad-hoc NETworks，VANESCO）的事实标准。它已经在GNU Radio SDR [1]上实现，它经历了帧解码/编码延迟。本文提出了一种基于FPGA的软件无线电作为解决方案，以加速帧解码的IEEE 802.11p波形。我们分享了在基于FPGA的嵌入式硬件架构上设计和验证SDR的经验。在FPGA Zynq平台的顶部，我们按照硬件/软件（HW/SW）协同设计方法移植了SDR GNU Radio。软件无线电系统的实时性能分析表明，具有FFT软件功能的OFDM均衡器是整个软件无线电接收机功能中最耗时的任务（34.74%）。我们建议使用FPGA Zynq的自由逻辑门作为硬件（HW）加速器来对FFT处理功能进行硬件加速。与纯软件实现相比，具有FFT子功能的硬件OFDM实现器可以加速SDR链处理。我们基于FPGA的SDR设计是提出嵌入式SDR的关键一步。它不仅是IEEE 802.11p标准的替代方案，也是任何基于OFDM的SDR的替代方案。
英文摘要：
Software Defined Radio (SDR) platforms are useful tools to design new wireless technologies or to improve specifications of existing ones. The IEEE 802.11p is the de-facto standard for Wireless Vehicular Ad-hoc NETworks (VANETs). It has been implemented on GNU Radio SDR [1], which experiences frames decoding/encoding latency. In this paper an FPGA based SDR is proposed as a solution to accelerate frame decoding of IEEE 802.11p waveforms. We share our experience in designing and validating an SDR on the top of real FPGA based embedded hardware architecture. On the top of an FPGA Zynq platform, we port an SDR GNU Radio following hardware/software (HW/SW) codesign approach. A real time profiling of the SDR system shows that the OFDM equalizer with FFT software function is the most time consuming task of the whole SDR receiver functions (34.74%). We suggest hardware acceleration of the FFT processing function using the free logic gates of the FPGA Zynq as a Hardware (HW) accelerator. The HW OFDM Equalizer with FFT sub-function could accelerate the SDR chain processing in comparison with a pure software implementation. Our FPGA based SDR design is a key step toward proposing an embedded SDR. It would be an alternative for not only the IEEE 802.11p standard but for any OFDM based SDR.
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