Quantum algorithms often use quantum RAMs (QRAM) for accessing information stored in a database-like manner. QRAMs have to be fast, resource efficient and fault-tolerant. The latter is often influenced by access speeds, because shorter times introduce less exposure of the stored information to noise. The total execution time of an algorithm depends on the QRAM access time which includes: 1) address translation time, and 2) effective query time. The bucket brigade QRAMs were proposed to achieve faster addressing at the cost of exponentially many ancillae. We illustrate a systematic method to significantly reduce the effective query time by using Clifford+T gate parallelism. The method does not introduce any ancillae qubits. Our parallelisation method is compatible with the surface code quantum error correction. We show that parallelisation is a result of advantageous Toffoli gate decomposition in terms of Clifford+T gates, and after addresses have been translated, we achieve theoretical $\mathcal{O}(1)$ parallelism for the effective queries. We conclude that, in theory: 1) fault-tolerant bucket brigade quantum RAM queries can be performed approximately with the speed of classical RAM; 2) the exponentially many ancillae from the bucket brigade addressing scheme are a trade-off cost for achieving exponential query speedup compared to quantum read-only memories whose queries are sequential by design. The methods to compile, parallelise and analyse the presented QRAM circuits were implemented in software which is available online.
In this short review I aim to explain how we can construct a circuit implementation of the bucketbrigade qRAM first proposed in [1]. Used with classical data, this qRAM model can be used incombination with the quantum accessible data structure [2] to prepare arbitrary quantum statesquickly and repeatedly, once the data to be prepared is in memory
We study the robustness of the bucket brigade quantum random access memory model introduced by Giovannetti, Lloyd, and Maccone [Phys. Rev. Lett. 100, 160501 (2008)]. Due to a result of Regev and Schiff [ICALP '08 pp. 773], we show that for a class of error models the error rate per gate in the bucket brigade quantum memory has to be of order $o(2^{-n/2})$ (where $N=2^n$ is the size of the memory) whenever the memory is used as an oracle for the quantum searching problem. We conjecture that this is the case for any realistic error model that will be encountered in practice, and that for algorit…
Classical simulation of amplitude-damped bucket-brigade quantum random access memories via predictable branch evolution
Institute of Artificial Intelligence, Hefei Comprehensive National Science Center（合肥综合性国家科学中心人工智能研究院）；Laboratory of Quantum Information, University of Science and Technology of China（中国科学技术大学量子信息实验室）；Anhui Province Key Laboratory of Quantum Network, University of Science and Technology of China（中国科学技术大学安徽省量子网络重点实验室）；Origin Quantum Computing Technology (Hefei) Co., Ltd.（本源量子计算技术（合肥）有限公司）
A novel concept of quantum random access memory (qRAM) employing a quantum walk is provided. Our qRAM relies on a bucket brigade scheme to access the memory cells. Introducing a bucket with chirality left and right as a quantum walker, and considering its quantum motion on a full binary tree, we can efficiently deliver the bucket to the designated memory cells, and fill the bucket with the desired information in the form of quantum superposition states. Our procedure has several advantages. First, we do not need to place any quantum devices at the nodes of the binary tree, and hence in our qRA…
Quantum random access memory (QRAM)--memory which stores classical data but allows queries to be performed in superposition--is required for the implementation of numerous quantum algorithms. While naive implementations of QRAM are highly susceptible to decoherence and hence not scalable, it has been argued that the bucket brigade QRAM architecture [Giovannetti et al., Phys. Rev. Lett. 100 160501 (2008)] is highly resilient to noise, with the infidelity of a query scaling only logarithmically with the memory size. In prior analyses, however, this favorable scaling followed directly from the us…
A "bucket brigade" architecture for a quantum random memory of $N=2^n$ memory cells needs $n(n+5)/2$ times of quantum manipulation on control circuit nodes per memory call. Here we propose a scheme, in which only average $n/2$ times manipulation is required to accomplish a memory call. This scheme may significantly decrease the time spent on a memory call and the average overall error rate per memory call. A physical implementation scheme for storing an arbitrary state in a selected memory cell followed by reading it out is discussed.
A random access memory, or RAM, is a device that, when interrogated, returns the content of a memory location in a memory array. A quantum RAM, or qRAM, allows one to access superpositions of memory sites, which may contain either quantum or classical information. RAMs and qRAMs with n-bit addresses can access 2^n memory sites. Any design for a RAM or qRAM then requires O(2^n) two-bit logic gates. At first sight this requirement might seem to make large scale quantum versions of such devices impractical, due to the difficulty of constructing and operating coherent devices with large numbers of…
This is the second paper in a series of two. Using a multi-particle continuous-time quantum walk with two internal states, which has been formulated in the first paper (arXiv:2112.08119), we physically implement a quantum random access memory (qRAM). Data with address information are dual-rail encoded into quantum walkers. The walkers pass through perfect binary trees to access the designated memory cells and copy the data stored in the cells. A roundabout gate allocated at each node serves as a router to move the walker from the parent node to one of two child nodes, depending on the internal…
Technical analysis of the Resource-efficient Quantum Walkers Quantum Random Access Memory
Scuola Normale Superiore（比萨高等师范学院）；NEST-CNR Scuola Normale Superiore（NEST-意大利国家研究委员会比萨高等师范学院）；Dept. of Mech. Eng., Massachusetts Institute of Technology（麻省理工学院机械工程系）
