用于基于掩埋施主的器件的低热预算高k/金属表面栅
Low Thermal Budget High-k/Metal Surface Gate for Buried Donor-Based Devices
AI总结：
针对原子精度先进制造（APAM）施主器件与工业工艺不兼容、高低热预算工艺存在权衡的问题，研究人员开发了低热预算外延硅帽与Al₂O₃栅氧化层并集成单电子晶体管（SET）表征栅质量，发现栅调控受层缺陷限制，提出更先进的栅堆叠与工艺以提升未来原子精度器件性能。
摘要：
原子精度先进制造（APAM）可在掺杂浓度超过固溶度极限的原子级薄层中制备施主器件，催生独特的器件物理特性。这为将APAM用作探路平台以研究原子极限下的数字电子学提供了机遇。将晶体管尺寸缩小到更小正变得愈发困难且成本高昂，因此亟需研究可延伸至原子尺度的替代制造路径。APAM施主器件可借助扫描隧道显微镜（STM）制备，但目前这类器件与工业标准制造工艺尚不兼容。在用于限制掺杂剂扩散的低热预算（LT）工艺，与用于生长无缺陷外延硅层和栅氧化层的高热预算（HT）工艺之间存在权衡。为此，我们开发了一种LT外延硅帽层以及LT沉积的Al₂O₃栅氧化层，并将其与原子精度的单电子晶体管（SET）集成，我们将该SET用作静电计以表征栅堆叠的质量。表面栅控SET表现出预期的库仑阻塞行为。然而，栅极对SET的调控能力受限于SET上方各层中的缺陷，包括硅与氧化物之间的界面，以及硅帽层中的结构和化学缺陷。我们提出了一种更先进的栅堆叠结构和工艺流程，预计可提升未来原子精度器件的性能。
英文摘要：
Atomic precision advanced manufacturing (APAM) offers creation of donor devices in an atomically thin layer doped beyond the solid solubility limit, enabling unique device physics. This presents an opportunity to use APAM as a pathfinding platform to investigate digital electronics at the atomic limit. Scaling to smaller transistors is increasingly difficult and expensive, necessitating the investigation of alternative fabrication paths that extend to the atomic scale. APAM donor devices can be created using a scanning tunneling microscope (STM). However, these devices are not currently compatible with industry standard fabrication processes. There exists a tradeoff between low thermal budget (LT) processes to limit dopant diffusion and high thermal budget (HT) processes to grow defect-free layers of epitaxial Si and gate oxide. To this end, we have developed an LT epitaxial Si cap and LT deposited Al2O3 gate oxide integrated with an atomically precise single-electron transistor (SET) that we use as an electrometer to characterize the quality of the gate stack. The surface-gated SET exhibits the expected Coulomb blockade behavior. However, the leverage of the gate over the SET is limited by defects in the layers above the SET, including interfaces between the Si and oxide, and structural and chemical defects in the Si cap. We propose a more sophisticated gate stack and process flow that is predicted to improve performance in future atomic precision devices.
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