利用内置的传感器和深度学习检测智能手机冒名顶替者
Smartphone Impostor Detection with Built-in Sensors and Deep Learning
摘要：
在本文中，我们表明，基于传感器的冒名顶替者检测与深度学习可以实现良好的冒名顶替者检测精度在较低的硬件成本相比，过去的工作基于传感器的用户认证（逆问题），使用更传统的机器学习算法。虽然这些方法使用其他智能手机用户的传感器数据来构建（用户，非用户）分类模型，但我们进一步表明，仅使用合法用户的传感器数据仍然可以实现非常好的准确性，同时保护用户传感器数据的隐私（行为生物识别）。对于这个用例，一个关键的贡献是表明，通过比较预测误差分布，可以显着提高递归神经网络（RNN）深度学习模型的检测精度。这需要生成和比较经验概率分布，我们在一个有效的硬件设计中显示。另一个新颖的贡献是SID（智能手机冒名顶替者检测）的设计，这是一种极简的硬件加速器，可以集成到未来的智能手机中，用于不同场景的高效冒名顶替者检测。我们的SID模块可以实现许多常见的机器学习和深度学习算法。SID在并行性和性能方面也是可扩展的，并且易于编程。我们展示了SID的FPGA原型，它可以提供足够的性能用于实时冒名顶替者检测，具有非常低的硬件复杂度和功耗（比相关的面向性能的FPGA加速器低一到两个数量级）。我们还表明，SID的FPGA实现消耗64.41倍的能量比使用CPU与GPU的实现。
英文摘要：
In this paper, we show that sensor-based impostor detection with deep learning can achieve excellent impostor detection accuracy at lower hardware cost compared to past work on sensor-based user authentication (the inverse problem) which used more conventional machine learning algorithms. While these methods use other smartphone users' sensor data to build the (user, non-user) classification models, we go further to show that using only the legitimate user's sensor data can still achieve very good accuracy while preserving the privacy of the user's sensor data (behavioral biometrics). For this use case, a key contribution is showing that the detection accuracy of a Recurrent Neural Network (RNN) deep learning model can be significantly improved by comparing prediction error distributions. This requires generating and comparing empirical probability distributions, which we show in an efficient hardware design. Another novel contribution is in the design of SID (Smartphone impostor Detection), a minimalist hardware accelerator that can be integrated into future smartphones for efficient impostor detection for different scenarios. Our SID module can implement many common Machine Learning and Deep Learning algorithms. SID is also scalable in parallelism and performance and easy to program. We show an FPGA prototype of SID, which can provide more than enough performance for real-time impostor detection, with very low hardware complexity and power consumption (one to two orders of magnitude less than related performance-oriented FPGA accelerators). We also show that the FPGA implementation of SID consumes 64.41X less energy than an implementation using the CPU with a GPU.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
