Fast inference of Boosted Decision Trees in FPGAs for particle physics
European Organization for Nuclear Research (CERN)（欧洲核子研究组织（CERN））；Columbia University（哥伦比亚大学）；University of California San Diego（加利福尼亚大学圣迭戈分校）；Massachusetts Institute of Technology（麻省理工学院）；Rhodes College（罗德学院）；Fermi National Accelerator Laboratory（费米国家加速器实验室）；Institute of Physics Belgrade（贝尔格莱德物理研究所）；University of Illinois at Chicago（伊利诺伊大学芝加哥分校）
英文摘要：
We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the translation of a trained model into FPGA firmware through an automated conversion process. Thanks to its fully on-chip implementation, hls4ml performs inference of Boosted Decision Tree models with extremely low latency. With a typical latency less than 100 ns, this solution is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger system of a collider experiment. These developments open up prospects for physicists to deploy BDTs in FPGAs for identifying the origin of jets, better reconstructing the energies of muons, and enabling better selection of rare signal processes.
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