SPARTA：加速器地址转换的分而治之方法
SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators
摘要：
虚拟内存（VM）对于硬件加速器的可用性和可编程性至关重要。不幸的是，高效地实现加速器VM是具有挑战性的，因为面积和功率限制使得难以采用通用CPU中使用的大型多级TLB。最近的研究建议提倡对虚拟地址到物理地址映射的许多限制，以便减小TLB大小或增加其范围。然而，这样的限制是没有吸引力的，因为它们放弃了传统VM的许多原始优点，例如请求分页和写时复制。我们提出了SPARTA，一个分而治之的方法来解决地址翻译。SPARTA将地址转换分为加速器端和内存端。加速器端转换硬件由一个仅覆盖加速器缓存层次结构（如果有的话）的小型TLB组成，而主内存访问的转换由共享内存端TLB执行。在存储器侧执行存储器访问的转换允许SPARTA将数据获取与转换重叠，并避免复制加速器之间共享的数据的TLB条目。为了进一步提高内存端翻译的性能和效率，SPARTA对内存空间进行逻辑分区，将翻译委托给小型高效的每分区翻译硬件。我们对索引遍历加速器的评估表明，SPARTA几乎消除了翻译开销，平均减少了30倍以上（高达47倍），性能提高了57%。与此同时，SPARTA只需要最少的加速器端转换硬件，减少了系统中TLB条目的总数，随着内存大小适度扩展，并保留了所有关键的VM功能。
英文摘要：
Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TLBs used in general-purpose CPUs. Recent research proposals advocate a number of restrictions on virtual-to-physical address mappings in order to reduce the TLB size or increase its reach. However, such restrictions are unattractive because they forgo many of the original benefits of traditional VM, such as demand paging and copy-on-write. We propose SPARTA, a divide and conquer approach to address translation. SPARTA splits the address translation into accelerator-side and memory-side parts. The accelerator-side translation hardware consists of a tiny TLB covering only the accelerator's cache hierarchy (if any), while the translation for main memory accesses is performed by shared memory-side TLBs. Performing the translation for memory accesses on the memory side allows SPARTA to overlap data fetch with translation, and avoids the replication of TLB entries for data shared among accelerators. To further improve the performance and efficiency of the memory-side translation, SPARTA logically partitions the memory space, delegating translation to small and efficient per-partition translation hardware. Our evaluation on index-traversal accelerators shows that SPARTA virtually eliminates translation overhead, reducing it by over 30x on average (up to 47x) and improving performance by 57%. At the same time, SPARTA requires minimal accelerator-side translation hardware, reduces the total number of TLB entries in the system, gracefully scales with memory size, and preserves all key VM functionalities.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
