arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2001.05348cs.NEcs.LGstat.ML

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

Institute of Industrial Science, The University of Tokyo(东京大学生产技术研究所);NEC Corporation(日本电气股份有限公司);Interdisciplinary Graduate School of Engineering Sciences, Kyushu University(九州大学工学研究院跨学科工学研究科);Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology(九州工业大学生命科学与系统工程研究生院);International Research Center for Neurointelligence (WPI-IRCN), The University of Tokyo Institutes for Advanced Study, The University of Tokyo(东京大学高等研究院神经智能国际研究中心(WPI-IRCN))

Yusuke Sakemi, Kai Morino, Takashi Morie, Kazuyuki Aihara

英文摘要:

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms, but also energy-efficient computational models when implemented in VLSI circuits. In this paper, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultra-high energy efficiency can be achieved. We also propose several techniques to improve the performance on a recognition task, and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST dataset. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.

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