基于FPGA的结构稀疏卷积神经网络硬件加速器
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
摘要：
深度卷积神经网络（CNN）在广泛的应用中实现了最先进的性能。然而，更深的CNN模型，这通常是计算消耗，广泛需要复杂的人工智能（AI）任务。虽然最近的研究进展网络压缩，如修剪已经成为一个有前途的方向，以减轻计算负担，现有的加速器仍然无法完全利用稀疏性的好处，由于修剪造成的不规则性。另一方面，现场可编程门阵列（FPGA）已被视为CNN推理加速的有前途的硬件平台。然而，大多数现有的FPGA加速器集中在密集的CNN，不能解决不规则性问题。在本文中，我们提出了一个稀疏的明智的卷积，跳过处理乘法和累加（MAC）与零权重的周期，并利用数据统计，以最大限度地减少能量通过零门，以避免不必要的计算。所提出的稀疏型卷积导致低带宽需求和高数据共享。然后，我们设计了一个FPGA加速器包含一个向量发生器模块（VGM），它可以匹配之间的索引稀疏权重和输入激活根据所提出的算法。实验结果表明，在Xilinx ZCU 102上，AlexNet和VGG-16的性能分别达到987 imag/s和48 imag/s，与之前的CNN FPGA加速器相比，其加速比为1.5倍至6.7倍，能效为2.0倍至6.2倍。
英文摘要：
Deep Convolutional Neural Networks (CNNs) have achieved state-of-the-art performance in a wide range of applications. However, deeper CNN models, which are usually computation consuming, are widely required for complex Artificial Intelligence (AI) tasks. Though recent research progress on network compression such as pruning has emerged as a promising direction to mitigate computational burden, existing accelerators are still prevented from completely utilizing the benefits of leveraging sparsity owing to the irregularity caused by pruning. On the other hand, Field-Programmable Gate Arrays (FPGAs) have been regarded as a promising hardware platform for CNN inference acceleration. However, most existing FPGA accelerators focus on dense CNN and cannot address the irregularity problem. In this paper, we propose a sparse wise dataflow to skip the cycles of processing Multiply-and-Accumulates (MACs) with zero weights and exploit data statistics to minimize energy through zeros gating to avoid unnecessary computations. The proposed sparse wise dataflow leads to a low bandwidth requirement and a high data sharing. Then we design an FPGA accelerator containing a Vector Generator Module (VGM) which can match the index between sparse weights and input activations according to the proposed dataflow. Experimental results demonstrate that our implementation can achieve 987 imag/s and 48 imag/s performance for AlexNet and VGG-16 on Xilinx ZCU102, respectively, which provides 1.5x to 6.7x speedup and 2.0x to 6.2x energy-efficiency over previous CNN FPGA accelerators.
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