二值化神经网络的差分半导体电阻存储阵列数字生物可行实现
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays
摘要：
大脑以极低的能量消耗执行智能任务。这项工作的灵感来自大脑用来实现这种能量效率的两种策略：计算和记忆功能之间没有分离，以及依赖低精度计算。电阻式存储器技术的出现确实提供了在硬件中紧密地共同集成逻辑和存储器的机会。并行地，最近提出的二值化神经网络的概念，其中乘法被异或非（XNOR）逻辑门取代，提供了一种使用非常低精度计算来实现人工智能的方法。因此，在这项工作中，我们提出了一种策略，以实现低能量二进制神经网络，它采用了大脑启发的概念，同时保留了数字电子产品的能源效益。我们设计，制造和测试的存储器阵列，包括外围和检测电路，优化这个存内计算计划。我们的电路采用氧化铪电阻存储器集成在后端线的130纳米CMOS工艺，在一个两个晶体管-两个电阻器单元，它允许执行的神经网络的异或操作直接在读出放大器。我们表明，广泛的电气测量的基础上，我们的设计允许减少突触权重的位错误的量，而不使用正式的纠错码。我们设计了一个完整的系统使用这个存储器阵列。我们在标准的机器学习任务（MNIST，CIFAR-10，ImageNet和ECG任务）上显示，该系统对比特错误具有固有的弹性。我们的证据表明，它的能量消耗是有吸引力的相比，更标准的方法，它可以使用的内存设备的制度，他们表现出特别低的编程能量和高耐力。
英文摘要：
The brain performs intelligent tasks with extremely low energy consumption. This work takes inspiration from two strategies used by the brain to achieve this energy efficiency: the absence of separation between computing and memory functions, and the reliance on low precision computation. The emergence of resistive memory technologies indeed provides an opportunity to co-integrate tightly logic and memory in hardware. In parallel, the recently proposed concept of Binarized Neural Network, where multiplications are replaced by exclusive NOR (XNOR) logic gates, offers a way to implement artificial intelligence using very low precision computation. In this work, we therefore propose a strategy to implement low energy Binarized Neural Networks, which employs brain-inspired concepts, while retaining energy benefits from digital electronics. We design, fabricate and test a memory array, including periphery and sensing circuits, optimized for this in-memory computing scheme. Our circuit employs hafnium oxide resistive memory integrated in the back end of line of a 130 nanometer CMOS process, in a two transistors - two resistors cell, which allows performing the exclusive NOR operations of the neural network directly within the sense amplifiers. We show, based on extensive electrical measurements, that our design allows reducing the amount of bit errors on the synaptic weights, without the use of formal error correcting codes. We design a whole system using this memory array. We show on standard machine learning tasks (MNIST, CIFAR-10, ImageNet and an ECG task) that the system has an inherent resilience to bit errors. We evidence that its energy consumption is attractive compared to more standard approaches, and that it can use the memory devices in regimes where they exhibit particularly low programming energy and high endurance.
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