3D- aCortex：基于商用3D- NAND闪存的超紧凑节能神经计算平台
3D-aCortex: An Ultra-Compact Energy-Efficient Neurocomputing Platform Based on Commercial 3D-NAND Flash Memories
摘要：
本文的第一个贡献是基于现有的3D-NAND闪存块开发了非常密集、节能的混合信号矢量乘矩阵乘法（VMM）电路，而无需对其进行任何修改。这种兼容性是通过使用时域编码的VMM设计来实现的。我们的详细模拟已经示出，例如，使用在55 nm技术节点中设计的市售的64层栅极全包围macaroni型3D-NAND存储器块的200元素向量的5位VMM可以提供0.14 um 2/字节的前所未有的面积效率和~10 fJ/Op的能量效率，包括输入/输出和其他外围电路开销。我们的第二个主要贡献是开发3D-aCortex，这是一种多用途神经形态推理处理器，它利用所提出的3D-VMM块作为其核心处理单元。我们已经进行了严格的性能模拟，这样的处理器上的电路和系统的水平，考虑到非理想的，如漏极诱导势垒降低，电容耦合，电荷注入，寄生效应，工艺变化，和噪声。我们对3D-aCortex进行的几个最先进的神经形态网络基准测试的建模表明，它可以提供创纪录的4.34 MB/mm 2的存储效率，70.43 TOps/J的峰值能量效率，以及高达10.66 TOps/s的计算吞吐量。通过主动共享VMM外围电路，存储效率可以进一步提高7倍，但代价是能量效率和吞吐量略有下降。
英文摘要：
The first contribution of this paper is the development of extremely dense, energy-efficient mixed-signal vector-by-matrix-multiplication (VMM) circuits based on the existing 3D-NAND flash memory blocks, without any need for their modification. Such compatibility is achieved using time-domain-encoded VMM design. Our detailed simulations have shown that, for example, the 5-bit VMM of 200-element vectors, using the commercially available 64-layer gate-all-around macaroni-type 3D-NAND memory blocks designed in the 55-nm technology node, may provide an unprecedented area efficiency of 0.14 um2/byte and energy efficiency of ~10 fJ/Op, including the input/output and other peripheral circuitry overheads. Our second major contribution is the development of 3D-aCortex, a multi-purpose neuromorphic inference processor that utilizes the proposed 3D-VMM blocks as its core processing units. We have performed rigorous performance simulations of such a processor on both circuit and system levels, taking into account non-idealities such as drain-induced barrier lowering, capacitive coupling, charge injection, parasitics, process variations, and noise. Our modeling of the 3D-aCortex performing several state-of-the-art neuromorphic-network benchmarks has shown that it may provide the record-breaking storage efficiency of 4.34 MB/mm2, the peak energy efficiency of 70.43 TOps/J, and the computational throughput up to 10.66 TOps/s. The storage efficiency can be further improved seven-fold by aggressively sharing VMM peripheral circuits at the cost of slight decrease in energy efficiency and throughput.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
