解决DRAM子系统中的多位/符号错误
Addressing multiple bit/symbol errors in DRAM subsystem
摘要：
随着DRAM技术继续朝着更小的特征尺寸和增加的密度发展，DRAM子系统中的故障变得更加严重。当前的服务器大多使用基于CHIPKILL的方案来容忍每个DRAM节拍高达一个/两个符号错误。由于多个数据总线和芯片中的故障而产生的多符号错误可能不会被这些方案检测到。在本文中，我们介绍了单符号校正多符号检测（SSCMSD）-一种新的错误处理方案，以纠正单符号错误和检测多符号错误。我们的方案利用哈希结合纠错码（ECC），以避免沉默的数据损坏（SDC）。SSCMSD还可以增强检测地址位中的错误的能力。我们采用32位CRC和Reed-Solomon码来实现基于x4的DDRx系统的SSCMSD。我们的仿真结果表明，该方案有效地防止SDC在存在多个符号错误。我们的新颖设计使我们能够在不引入额外读取延迟的情况下实现这一点。此外，我们需要每列19个芯片（存储开销为18.75%），76条数据总线线和存储器控制器处的附加散列逻辑。
英文摘要：
As DRAM technology continues to evolve towards smaller feature sizes and increased densities, faults in DRAM subsystem are becoming more severe. Current servers mostly use CHIPKILL based schemes to tolerate up-to one/two symbol errors per DRAM beat. Multi-symbol errors arising due to faults in multiple data buses and chips may not be detected by these schemes. In this paper, we introduce Single Symbol Correction Multiple Symbol Detection (SSCMSD) - a novel error handling scheme to correct single-symbol errors and detect multi-symbol errors. Our scheme makes use of a hash in combination with Error Correcting Code (ECC) to avoid silent data corruptions (SDCs). SSCMSD can also enhance the capability of detecting errors in address bits. We employ 32-bit CRC along with Reed-Solomon code to implement SSCMSD for a x4 based DDRx system. Our simulations show that the proposed scheme effectively prevents SDCs in the presence of multiple symbol errors. Our novel design enabled us to achieve this without introducing additional READ latency. Also, we need 19 chips per rank (storage overhead of 18.75 percent), 76 data bus-lines and additional hash-logic at the memory controller.
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