HTS：一个异构系统的硬件任务调度器
HTS: A Hardware Task Scheduler for Heterogeneous Systems
摘要：
随着摩尔缩放时代的结束，应用特定的硬件加速器出现作为一个有吸引力的方式来提高我们的计算系统的性能和功率效率。具有大量硬件加速器以及多个通用CPU的大规模异构系统是一个有前途的方向，但在加速器上的任务的运行时调度和加速器的设计粒度方面提出了一些挑战。本文通过开发一个示例异构系统来解决这些挑战，该系统使多个应用程序能够共享可用的加速器。我们建议在较低的抽象设计加速器，使应用程序被分解成可以映射到几个加速器的任务。我们观察到，几个现实生活中的工作负载可以被分解为在许多工作负载之间共享的常见原语。最后，我们提出并设计了一个硬件任务调度器的启发，在乱序超标量处理器的硬件加速器，以有效地利用系统中的加速器，调度任务的乱序，甚至投机。我们评估所提出的系统在现实生活中和综合基准的基础上数字信号处理~（DSP）的应用。与在具有顺序调度的系统上执行基准测试相比，所提出的调度器在性能上实现了高达12倍的改进。
英文摘要：
As the Moore's scaling era comes to an end, application specific hardware accelerators appear as an attractive way to improve the performance and power efficiency of our computing systems. A massively heterogeneous system with a large number of hardware accelerators along with multiple general purpose CPUs is a promising direction, but pose several challenges in terms of the run-time scheduling of tasks on the accelerators and design granularity of accelerators. This paper addresses these challenges by developing an example heterogeneous system to enable multiple applications to share the available accelerators. We propose to design accelerators at a lower abstraction to enable applications to be broken down into tasks that can be mapped on several accelerators. We observe that several real-life workloads can be broken down into common primitives that are shared across many workloads. Finally, we propose and design a hardware task scheduler inspired by the hardware schedulers in out-of-order superscalar processors to efficiently utilize the accelerators in the system by scheduling tasks in out-of-order and even speculatively. We evaluate the proposed system on both real-life and synthetic benchmarks based on Digital Signal Processing~(DSP) applications. Compared to executing the benchmark on a system with sequential scheduling, proposed scheduler achieves up to 12x improvement in performance.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
