优化无路由片上网络设计：一个基于学习的创新框架
Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework
摘要：
将机器学习应用于建筑设计提供了具有广泛应用前景的机会。特别是最近的深度强化学习（DRL）技术，能够在传统设计策略可能不充分的巨大设计空间中进行有效探索。本文提出了一种新的深度加固框架，以无路由器片上网络（NoC）作为评估案例研究。新框架成功地解决了先前的设计方法由于随机搜索而不可靠或由于严重的设计空间限制而不灵活的问题。该框架学习（近）最佳的环路布局与各种设计约束的无路由片上网络。一个深度神经网络开发使用并行线程，有效地探索巨大的无路由器片上网络设计空间与蒙特卡洛搜索树。实验结果表明，与传统网格相比，所提出的深度强化学习（DRL）无路由器设计实现了3.25倍的吞吐量增加，1.6倍的数据包延迟减少，和5倍的功耗降低。与最先进的无路由器NoC相比，DRL实现了1.47倍的吞吐量增加，1.18倍的数据包延迟减少，以及1.14倍的平均跳数减少，尽管功耗略高。
英文摘要：
Machine learning applied to architecture design presents a promising opportunity with broad applications. Recent deep reinforcement learning (DRL) techniques, in particular, enable efficient exploration in vast design spaces where conventional design strategies may be inadequate. This paper proposes a novel deep reinforcement framework, taking routerless networks-on-chip (NoC) as an evaluation case study. The new framework successfully resolves problems with prior design approaches being either unreliable due to random searches or inflexible due to severe design space restrictions. The framework learns (near-)optimal loop placement for routerless NoCs with various design constraints. A deep neural network is developed using parallel threads that efficiently explore the immense routerless NoC design space with a Monte Carlo search tree. Experimental results show that, compared with conventional mesh, the proposed deep reinforcement learning (DRL) routerless design achieves a 3.25x increase in throughput, 1.6x reduction in packet latency, and 5x reduction in power. Compared with the state-of-the-art routerless NoC, DRL achieves a 1.47x increase in throughput, 1.18x reduction in packet latency, and 1.14x reduction in average hop count albeit with slightly more power overhead.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
