约瑟夫森结超导随机存储器的超大规模集成
Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories
摘要：
已设计、制造并成功展示了功能密度高达$1 Mbit/cm^2$的涡旋过渡（VT）存储单元阵列。这一进展归功于麻省理工学院林肯实验室在设计优化和超导体电子制造方面取得的最新进展。作为一个起点，我们开发了一个示范阵列的VT细胞的100- $μA/μm^2$麻省理工学院LL制造工艺SFQ 5ee与8铌层。所研究的具有双结非破坏性读出的双结存储器单元占据$168 μm^2$，导致超过$0.5 Mbit/cm^2$功能密度。然后，我们通过利用具有临界电流密度的自分流约瑟夫森结（JJ）、$600 μA/μm^2$的$J_c$和消除分流电阻器将单元面积减小到$99 μm^2$（对应于超过$0.9 Mbit/cm^2$功能密度）。所制造的高$J_c$存储器单元是完全可操作的，并且具有宽的读/写电流裕度，非常接近理论预测值。我们讨论了进一步提高超导存储器和逻辑电路集成规模的方法：a）通过使用软磁材料使超导Transformers小型化; b）通过使用类似于变厚度桥的平面高$J_c$结来减小JJ面积。
英文摘要：
Arrays of Vortex Transitional (VT) memory cells with functional density up to $1 Mbit/cm^2$ have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-$μA/μm^2$ MIT LL fabrication process SFQ5ee with 8 niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied $168 μm^2$, resulting in an over $0.5 Mbit/cm^2$ functional density. Then, we reduced the cell area down to $99 μm^2$ (corresponding to over $0.9 Mbit/cm^2$ functional density) by utilizing self-shunted Josephson Junctions (JJs) with critical current density, $J_c$ of $600 μA/μm^2$ and eliminating shunt resistors. The fabricated high-$J_c$ memory cells were fully operational and possessed wide Read/Write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: a) miniaturization of superconducting transformers by using soft magnetic materials; b) reduction of JJ area by using planar high-$J_c$ junctions similar to variable thickness bridges.
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