全自检电路的自动综合
Automatic Synthesis of Totally Self-Checking Circuits
摘要：
完全自检（TSC）电路与运行基于分布式种群的随机优化算法的计算机网格合成。所提出的方法是第一个自动合成TSC电路从任意逻辑，因为所有以前的方法都不能保证检查器是自测试（ST）的电路与有限的输出码空间。所提出的方法合成的电路具有显着降低的开销比以前报道的最好的一组11个常用的基准。整个集合的平均开销是重复和比较开销的23%，而集合中以前报告的最佳值的平均开销为69%。提出的方法是并发错误检测（CED）的一个突破。生产的高效、新颖的设计是针对每个电路的功能量身定制的，而不是受到特定模块化CED设计方法的限制。结果合成使用两个输入门和TSC相对于所有门输入和输出固定故障。该方法可用于添加CED与或不修改原始逻辑，并可以推广到任何实现技术和故障模型。一个例子电路进行了分析，并严格证明是TSC。
英文摘要：
Totally self-checking (TSC) circuits are synthesised with a grid of computers running a distributed population based stochastic optimisation algorithm. The presented method is the first to automatically synthesise TSC circuits from arbitrary logic as all previous methods fail to guarantee the checker is self-testing (ST) for circuits with limited output codespaces. The circuits synthesised by the presented method have significantly lower overhead than the previously reported best for every one of a set of 11 frequently used benchmarks. Average overhead across the entire set is 23% of duplication and comparison overhead, compared with an average of 69% for the previous best reported values across the set. The methodology presented represents a breakthrough in concurrent error detection (CED). The highly efficient, novel designs produced are tailored to each circuit's function, rather than being constrained by a particular modular CED design methodology. Results are synthesised using two-input gates and are TSC with respect to all gate input and output stuck-at faults. The method can be used to add CED with or without modifications to the original logic, and can be generalised to any implementation technology and fault model. An example circuit is analysed and rigorously proven to be TSC.
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