自定义指令加速Viterbi算法
Accelerating Viterbi Algorithm using Custom Instruction Approach
摘要：
近年来，通信网络中的解码算法变得越来越复杂，目的是在正确解码接收到的消息时实现高可靠性。这些解码算法涉及需要高性能计算硬件的计算上复杂的操作，这通常是昂贵的。一种具有成本效益的解决方案是通过为解码算法的计算部分创建新的自定义指令来增强处理器的指令集架构（ISA）。在本文中，我们提出了利用自定义指令的方法来有效地实现广泛使用的Viterbi解码算法，通过添加汇编语言指令的ISA的DLX，PicoJava II和NIOS II处理器，这代表RISC，堆栈和FPGA为基础的软核处理器架构，分别。通过使用自定义指令方法，Viterbi算法的执行时间在DLX和PicoJava II中显著缩短了约3倍，在NIOS II中缩短了2倍。
英文摘要：
In recent years, the decoding algorithms in communication networks are becoming increasingly complex aiming to achieve high reliability in correctly decoding received messages. These decoding algorithms involve computationally complex operations requiring high performance computing hardware, which are generally expensive. A cost-effective solution is to enhance the Instruction Set Architecture (ISA) of the processors by creating new custom instructions for the computational parts of the decoding algorithms. In this paper, we propose to utilize the custom instruction approach to efficiently implement the widely used Viterbi decoding algorithm by adding the assembly language instructions to the ISA of DLX, PicoJava II and NIOS II processors, which represent RISC, stack and FPGA-based soft-core processor architectures, respectively. By using the custom instruction approach, the execution time of the Viterbi algorithm is significantly improved by approximately 3 times for DLX and PicoJava II, and by 2 times for NIOS II.
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