CIDPro：动态程序多样化的定制指令
CIDPro: Custom Instructions for Dynamic Program Diversification
摘要：
定时侧信道攻击由于其易访问性而对嵌入式系统构成了重大威胁。我们提出CIDPro，一个框架，依赖于动态的程序多样化，以减轻定时边信道泄漏。该框架集成了广泛使用的LLVM编译器基础设施和日益流行的RISC-V FPGA软处理器。编译器在程序的安全关键段中自动生成自定义指令，指令在RISC-V自定义协处理器上执行，以在每个执行实例上产生多样化的时序特性。CIDPro已在Zynq 7000 XC 7Z 020 FPGA器件上实现，以研究性能开销和安全权衡。实验结果表明，我们的解决方案可以实现80%和86%的定时侧信道容量减少两个基准与可接受的性能开销相比，现有的解决方案。此外，所提出的方法只会导致整个RISC-V系统的1%切片的硬件面积开销可以忽略不计。
英文摘要：
Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA soft-processor. The compiler automatically generates custom instructions in the security critical segments of the program, and the instructions execute on the RISC-V custom co-processor to produce diversified timing characteristics on each execution instance. CIDPro has been implemented on the Zynq7000 XC7Z020 FPGA device to study the performance overhead and security tradeoffs. Experimental results show that our solution can achieve 80% and 86% timing side-channel capacity reduction for two benchmarks with an acceptable performance overhead compared to existing solutions. In addition, the proposed method incurs only a negligible hardware area overhead of 1% slices of the entire RISC-V system.
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