器件设计对Si/SiO $_2$单电子器件电荷偏移漂移的影响
Effect of device design on charge offset drift in Si/SiO$_2$ single electron devices
摘要：
我们测量了Si/SiO $_2$单电子器件（SED）的低频时间不稳定性，称为电荷偏移漂移，有和没有一个整体的多晶硅顶栅。我们发现，与多晶硅顶栅的SED具有显着更少的电荷偏移漂移，表现出更少的孤立跳跃和一个稳定的平均值的波动减少了两个因素。所观察到的减少可以通过缺陷和量子点之间的互电容$C_m$的静电减少以及由于顶栅导致的总缺陷电容$C_d$的增加来解释。这些结果偏离了公认的理解，即SED中的电荷偏移漂移水平由固有材料特性决定，也迫使考虑器件设计。我们希望这些结果是重要的，在发展中的应用，从量子信息计量学或任何地方的电荷噪声或器件的可集成性是一个挑战的SED。
英文摘要：
We have measured the low-frequency time instability known as charge offset drift of Si/SiO$_2$ single electron devices (SEDs) with and without an overall poly-Si top gate. We find that SEDs with a poly-Si top gate have significantly less charge offset drift, exhibiting fewer isolated jumps and a factor of two reduction in fluctuations about a stable mean value. The observed reduction can be accounted for by the electrostatic reduction in the mutual capacitance $C_m$ between defects and the quantum dot, and increase in the total defect capacitance $C_d$ due to the top gate. These results depart from the accepted understanding that the level of charge offset drift in SEDs is determined by the intrinsic material properties, forcing consideration of the device design as well. We expect these results to be of importance in developing SEDs for applications from quantum information to metrology or wherever charge noise or integrability of devices is a challenge.
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