16 nm FinFET中用于极化码的5.16 Gbps解码器ASIC
A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET
摘要：
Polar Code已被选为5G标准。然而，目前只有少数几个ASIC芯片实现了解码器，并且都不支持列表长度L > 4和码长N > 1024。本文提出了一种用于极化码的三种解码器的ASIC实现：连续消除（SC）解码器、灵活解码器和超可靠解码器。这些解码器都是基于SC的解码器，支持的列表大小分别为1，8，32，码长分别为2^15，2^14，2^11。该芯片采用16nm TSMC FinFET技术制造，时钟频率为1 Ghz。提出并采用优化技术来提高吞吐量。实验结果表明，该系统的吞吐量可以达到5.16Gbps。与已有的AISC译码器和综合译码器相比，该译码器具有更高的面积效率。
英文摘要：
Polar codes has been selected as 5G standard. However, only a couple of ASIC featuring decoders are fabricated,and none of them support list size L > 4 and code length N > 1024. This paper presents an ASIC implementation of three decoders for polar code: successive cancellation (SC) decoder, flexible decoder and ultra-reliable decoder. These decoders are all SC based decoder, supporting list size up to 1,8,32 and code length up to 2^15,2^14,2^11 respectively. This chip is fabricated in a 16nm TSMC FinFET technology, and can be clocked at 1 Ghz. Optimization techniques are proposed and employed to increase throughput. Experiment result shows that the throughput can achieve up to 5.16Gbps. Compared with fabricated AISC decoder and synthesized decoder in literature, the flexible decoder achieves higher area efficiency.
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