基于非对称网络的低本底中规模物理实验后端电子学
Back-end Electronics for Low Background and Medium Scale Physics Experiments Based on an Asymmetric Network
摘要：
本文介绍的探测器读出架构是为了中小型物理实验，有适度的带宽需求，和应用程序，需要一个最终的低背景放射性的部分接近探测器。简化读出系统和最小化材料预算的第一个想法是使用公共扇出结构来从检测器外后端电子器件传输前端电子器件的同步、配置和读出所需的所有流量。第二个想法是在每个前端卡和后端电子设备之间使用点对点链路，该链路以满足目标应用的相对较低的速度运行。这拓宽了通信链路的物理介质的可能选择，例如玻璃纤维、塑料光纤或铜。本文提出了一种通信协议，足以为拟议的非对称网络，并显示了后端单元的设计，能够控制32个前端单元在高达12.8 Gbps的总带宽使用廉价的商业FPGA模块，其中大量的常规I/O引脚接口的前端链路，而少数可用的每秒数吉比特能力的收发器影响与DAQ系统的上级的通信。
英文摘要：
The detector readout architecture introduced in this paper is intended for small to medium size physics experiments that have moderate bandwidth needs, and applications that require an ultimately low background radioactivity for the parts close to the detector. The first idea to simplify the readout system and minimize material budget is to use a common fanout structure to transport from the off-detector back-end electronics all the traffic required for the synchronization, configuration and readout of the front-end electronics. The second idea is to use between each front-end card and the back-end electronics a point-to-point link that runs at the relatively low speed that suffices for the target application. This broadens the possible choices for the physical media of the communication links, e.g. glass fiber, plastic optical fiber, or copper. This paper presents a communication protocol adequate for the proposed asymmetric network and shows the design of a back-end unit capable of controlling 32 front-end units at up to 12.8 Gbps of aggregate bandwidth using an inexpensive commercial FPGA module where the large number of regular I/O pins interface to the front-end links, while the few available multi-gigabit per second capable transceivers are affected to the communication with the upper stage of the DAQ system.
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