基于VLSI结构的紧凑型非RLL信标可见光通信发射机和接收机
VLSI Architecture of Compact Non-RLL Beacon-based Visible Light Communication Transmitter and Receiver
摘要：
本文首次介绍了紧凑型VLC发射机和接收机的几种硬件实现。与相关工作相比，我们的VLC发射机是非RLL的，这意味着即使没有RLL代码也可以保证闪烁抑制。特别地，我们已经利用预加扰器和极化编码器的集中式比特概率分布来创建非RLL闪烁缓解解决方案。此外，在接收端，提出了一个3位软判决滤波器来分析从实VLC信道接收到的信号，以提取对数似然比（LLR）值，并将其馈送到FEC解码器。因此，极化译码器的软译码可以被实现以改善VLC系统的误比特率（BER）性能。最后，我们介绍了一种新的超大规模集成电路（VLSI）结构的紧凑型VLC发射机和接收机，并综合我们的设计下FPGA/ASIC综合工具。由于非RLL的基础，我们的系统有一个明显的好码率和降低复杂度相比，其他基于RLL的接收机工作。同时，我们也给出了该架构的FPGA和ASIC综合结果，并从功耗、面积、单位比特能量等方面进行了评估。
英文摘要：
In this paper, we introduce a couple of hardware implementations of compact VLC transmitter and receiver for the first time. Compared with related works, our VLC transmitter is non-RLL one, that means flicker mitigation can be guaranteed even without RLL codes. In particular, we have utilized a centralized bit probability distribution of a prescrambler and a Polar encoder to create a non-RLL flicker mitigation solution. Moreover, at the receiver, a 3-bit soft-decision filter is proposed to analyze signals received from real VLC channel to extract log-likelihood ratio (LLR) values and feed them to the FEC decoder. Therefore, soft-decoding of Polar decoder can be implemented to improve the bit-error-rate (BER) performance of the VLC system. Finally, we introduce a novel very large scale integration (VLSI) architecture for the compact VLC transmitter and receiver; and synthesis our design under FPGA/ASIC synthesis tools. Due to the non-RLL basic, our system has an evidently good code-rate and a reduced-complexity compared with other RLL-based receiver works. Also, we present FPGA and ASIC synthesis results of the proposed architecture with evaluations of power consumption, area, energy-per-bits and so on.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
