多个并行RRAM作为训练SNN的突触模型的情况
A case for multiple and parallel RRAMs as synaptic model for training SNNs
摘要：
为了能够在脉冲神经网络硬件中密集集成模型突触，正在考虑各种纳米级器件。这样的设备，除了表现出尖峰时间相关的可塑性（STDP）之外，还需要高度可扩展，具有大的耐久性，并且需要低能量用于状态之间的转换。在这项工作中，我们首先介绍和经验确定两个新的规范SNN中的突触：每个突触的电导水平和最大学习率的数量。据我们所知，没有RRAM符合后一种规格。作为一种解决方案，我们建议使用多个PCMO-RRAM在突触内并行。在突触读取时，同时读取所有PCMO-RRAM，并且对于每个突触电导变化事件，仅针对从集合中随机挑选的一个RRAM启动电导STDP的机制。其次，为了验证我们的解决方案，我们实验证明了PCMO-RRAM电导的STDP，然后表明，由于大的学习率，单个PCMO-RRAM无法在SNN的训练中建模突触。正如预期的那样，随着更多的PCMO-RRAM被添加到突触，网络训练得到了改善。第四，我们讨论了电路的要求，实现这样的计划，得出结论，要求是在范围内。因此，我们的工作提出了可训练SNN中突触设备的规范，指出了最先进的突触竞争者的缺点，并提供了一种解决方案来满足规范，并讨论了实现该解决方案的外围电路。
英文摘要：
To enable a dense integration of model synapses in a spiking neural networks hardware, various nano-scale devices are being considered. Such a device, besides exhibiting spike-time dependent plasticity (STDP), needs to be highly scalable, have a large endurance and require low energy for transitioning between states. In this work, we first introduce and empirically determine two new specifications for an synapse in SNNs: number of conductance levels per synapse and maximum learning-rate. To the best of our knowledge, there are no RRAMs that meet the latter specification. As a solution, we propose the use of multiple PCMO-RRAMs in parallel within a synapse. While synaptic reading, all PCMO-RRAMs are simultaneously read and for each synaptic conductance-change event, the mechanism for conductance STDP is initiated for only one RRAM, randomly picked from the set. Second, to validate our solution, we experimentally demonstrate STDP of conductance of a PCMO-RRAM and then show that due to a large learning-rate, a single PCMO-RRAM fails to model a synapse in the training of an SNN. As anticipated, network training improves as more PCMO-RRAMs are added to the synapse. Fourth, we discuss the circuit-requirements for implementing such a scheme, to conclude that the requirements are within bounds. Thus, our work presents specifications for synaptic devices in trainable SNNs, indicates the shortcomings of state-of-art synaptic contenders, and provides a solution to extrinsically meet the specifications and discusses the peripheral circuitry that implements the solution.
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