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arXiv 1802.08601cs.ET
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8T SRAM单元作为超越von-Neumann计算的多位点积引擎

8T SRAM Cell as a Multi-bit Dot Product Engine for Beyond von-Neumann Computing

Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy

摘要:

大规模数字计算几乎完全依赖于冯-诺依曼体系结构,该体系结构包括用于存储和计算的单独单元。从存储器单元到计算核心的能量昂贵的数据传输导致众所周知的冯-诺依曼瓶颈。各种方法,旨在绕过冯诺依曼瓶颈正在广泛探讨的文献。新兴的非易失性忆阻技术已被证明在以原位方式计算模拟点积方面非常有效。点积的忆阻模拟计算导致比数字向量存储器中逐位布尔计算快得多的操作。然而,关于大规模制造的挑战加上忆阻器的有限耐久性已经阻碍了基于忆阻的计算解决方案的快速商业化。在这项工作中,我们表明,标准的8晶体管(8T)的数字SRAM阵列可以配置为一个类似于模拟的内存中的多位点积引擎。通过向8T SRAM阵列的读端口施加适当的模拟电压,并感测输出电流,可以实现近似模数点积引擎。我们提出了两种不同的配置,使多位点积计算在8T SRAM单元阵列,而不修改标准的位单元结构。由于我们的方案保留了标准的8T-SRAM阵列结构,因此它可以用作具有标准读写指令的存储元件,也可以用作按需模拟点积加速器。

英文摘要:

Large scale digital computing almost exclusively relies on the von-Neumann architecture which comprises of separate units for storage and computations. The energy expensive transfer of data from the memory units to the computing cores results in the well-known von-Neumann bottleneck. Various approaches aimed towards bypassing the von-Neumann bottleneck are being extensively explored in the literature. Emerging non-volatile memristive technologies have been shown to be very efficient in computing analog dot products in an in-situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bit-wise Boolean computations. However, challenges with respect to large scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive based computing solutions. In this work, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analog-like in-memory multi-bit dot product engine. By applying appropriate analog voltages to the read-ports of the 8T SRAM array, and sensing the output current, an approximate analog-digital dot-product engine can be implemented. We present two different configurations for enabling multi-bit dot product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read-write instructions, and also as an on-demand analog-like dot product accelerator.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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