阻性和电抗性负载对信号放大的影响
On the Effects of Resistive and Reactive Loads on Signal Amplification
摘要：
研究了无功负荷对放大的影响。采用简化的共发射极电路结构，分别得到了与时间无关和与时间相关的电压和电流方程。由于非线性，无法使用相量分析，电容器上的电压用相应的积分表示，这意味着采用数值方法。首先研究了纯阻性负载的影响，结果表明，晶体管等值线的扇形结构会严重扭曲放大，特别是对于小的$V_a$和大的$s$。发现总谐波失真不依赖于$V_a$，由$s$和负载电阻$R$确定。得到了电流增益与基极电流的关系式，结果表明，电流增益随$I_B$几乎完全线性地减小。值得注意的是，如果不超过最大功耗限制，则当$R=0$时，不会出现增益变化，因此可以获得完美的线性放大。容性负载意味着电路轨迹从直线分离为“椭圆”状回路。这意味着沿着该环路的上弧或下弧的增益不对称。通过使用随时间变化的电路方程，可以通过数值和解析近似来表明，至少对于所采用的电路和参数值，由容性负载引起的不对称性是不显著的。然而，容性负载将意味着输出电压和电流之间的滞后，从而意味着低通滤波。结果表明，较小的$V_a$和较大的$s$可以大大减少相位滞后，但代价是严重的失真。
英文摘要：
The effects of reactive loads into amplification is studied. A simplified common emitter circuit configuration was adopted and respective time-independent and time-dependent voltage and current equations were obtained. As phasor analysis cannot be used because of the non-linearity, the voltage at the capacitor was represented in terms of the respective integral, implying a numerical approach. The effect of purely resistive loads was investigated first, and it was shown that the fanned structure of the transistor isolines can severely distort the amplification, especially for $V_a$ small and $s$ large. The total harmonic distortion was found not to depend on $V_a$, being determined by $s$ and the load resistance $R$. An expression was obtained for the current gain in terms of the base current and it was shown that it decreases in an almost perfectly linearly fashion with $I_B$. Remarkably, no gain variation, and hence perfectly linear amplification, is obtained when $R=0$, provided maximum power dissipation limits are not exceeded. Capacitive loads imply the detachment of the circuit trajectory from a straight line to an "ellipsoidal"-like loop. This implies a gain asymmetry along upper or lower arcs of this loop. By using the time-dependent circuit equations, it was possible to show numerically and by an analytical approximation that, at least for the adopted circuit and parameter values, the asymmetry induced by capacitive loads is not substantial. However, capacitive loads will imply lag between the output voltage and current and, hence, low-pass filtering. It was shown that smaller $V_a$ and larger $s$ can substantially reduce the phase lag, but at the cost of severe distortion.
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