用于超低能耗计算的压控拓扑自旋开关--性能建模与基准测试
Voltage-Controlled Topological-Spin Switch for Ultra-Low-Energy Computing--Performance Modeling and Benchmarking
摘要：
提出了一种压控拓扑自旋开关（vTOPSS），该开关采用混合拓扑绝缘体-磁绝缘体多铁性结构，可以实现布尔逻辑运算，每比特能量小于10 aJ，能量延迟积为$10^{-27}$ J量级.该器件使用了拓扑绝缘体（TI），它具有最高的电场到自旋扭矩的转换效率，但在室温下观察到，和低力矩磁绝缘体（MI），可以快速响应给定的自旋扭矩。我们提出的vTOPSS的操作理论，开发其性能指标的分析模型，阐明尺寸和电压的性能缩放，和基准vTOPSS对现有的自旋为基础的CMOS器件。与现有的基于自旋的器件（例如全自旋逻辑和电荷自旋逻辑）相比，vTOPSS提供低100 $\times$的能量耗散和低（40-100）$\times$的能量延迟积。随着实验的进展和材料性能的改善，我们表明，vTOPSS的能量延迟产品可以降低到$10^{-29}$ Js，与现有的CMOS技术竞争。最后，我们建立的互连问题，占主导地位的CMOS逻辑的性能是相对不太重要的vTOPSS，这意味着高阻材料确实可以用来互连vTOPSS设备。
英文摘要：
A voltage-controlled topological-spin switch (vTOPSS) that uses a hybrid topological insulator-magnetic insulator multiferroic is presented that can implement Boolean logic operations with sub-10 aJ energy-per-bit and energy-delay product on the order of $10^{-27}$ Js. The device uses a topological insulator (TI), which has the highest efficiency of conversion of electric field to spin torque yet observed at room temperature, and a low-moment magnetic insulator (MI) that can respond rapidly to a given spin torque. We present the theory of operation of vTOPSS, develop analytic models of its performance metrics, elucidate performance scaling with dimensions and voltage, and benchmark vTOPSS against existing spin-based and CMOS devices. Compared to existing spin-based devices, such as all-spin logic and charge-spin logic, vTOPSS offers 100$\times$ lower energy dissipation and (40-100)$\times$ lower energy-delay product. With experimental advances and improved material properties, we show that the energy-delay product of vTOPSS can be lowered to $10^{-29}$ Js, competitive against existing CMOS technology. Finally, we establish that interconnect issues that dominate the performance in CMOS logic are relatively less significant for vTOPSS, implying that highly resistive materials can indeed be used to interconnect vTOPSS devices.
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