分析和减轻永久性故障对基于脉动阵列的神经网络加速器的影响
Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
摘要：
由于其日益普及和计算成本，深度神经网络（DNN）正成为硬件加速的目标。谷歌张量处理单元（TPU）采用的DNN加速的流行架构在其核心使用了基于脉动阵列的矩阵乘法单元。本文论述了高缺陷率技术的容错，脉动阵列为基础的DNN加速器的设计。为此，我们的经验表明，即使在极低的故障率（低至$0.006\%$）的基线TPU的分类精度显着下降。然后，我们提出了两种新的策略，故障感知修剪（FAP）和故障感知修剪+再训练（FAP+T），使TPU的故障率高达$50\%$，可以忽略不计的分类精度下降（低至$0.1\%$），没有运行时的性能开销。FAP+T确实在部署之前对每个TPU芯片引入了一次性的再训练惩罚，但我们提出了将这种一次性惩罚减少到12分钟以下的优化。然后，在TPU的整个操作寿命期间摊销惩罚。
英文摘要：
Due to their growing popularity and computational cost, deep neural networks (DNNs) are being targeted for hardware acceleration. A popular architecture for DNN acceleration, adopted by the Google Tensor Processing Unit (TPU), utilizes a systolic array based matrix multiplication unit at its core. This paper deals with the design of fault-tolerant, systolic array based DNN accelerators for high defect rate technologies. To this end, we empirically show that the classification accuracy of a baseline TPU drops significantly even at extremely low fault rates (as low as $0.006\%$). We then propose two novel strategies, fault-aware pruning (FAP) and fault-aware pruning+retraining (FAP+T), that enable the TPU to operate at fault rates of up to $50\%$, with negligible drop in classification accuracy (as low as $0.1\%$) and no run-time performance overhead. The FAP+T does introduce a one-time retraining penalty per TPU chip before it is deployed, but we propose optimizations that reduce this one-time penalty to under 12 minutes. The penalty is then amortized over the entire lifetime of the TPU's operation.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
