最优含亚稳性排序网络
Optimal Metastability-Containing Sorting Networks
摘要：
当违反了可编程元件的建立/保持时间时，它们可能变得亚稳态，即，进入既不是数字0也不是数字1的瞬态。一般来说，亚稳态是无法避免的，每当对模拟值进行离散测量时都会出现这个问题。然后，输出的亚稳定性反映了关于测量是否应该向上或向下舍入到下一个可能的测量结果的不确定性。令人惊讶的是，Lenzen和Medina（ASYNC 2016）表明可以包含亚稳态，即，测量值可以被正确地分类，而无需首先解决亚稳态。然而，他们的工作和Bund等人的最新技术（日期2017）都没有确定这种解决方案是否可以像标准排序网络一样小而快。我们表明，这确实是可能的，通过提供一个电路，排序格雷码输入（可能包含一个亚稳态位），并具有渐近最佳的深度和大小。具体地说，对于10通道排序网络和16位宽的输入，我们提高了48.46%的延迟和71.58%的面积比Bund等人。我们的模拟表明，直接的晶体管级优化可能会导致性能与标准（不含）的解决方案。
英文摘要：
When setup/hold times of bistable elements are violated, they may become metastable, i.e., enter a transient state that is neither digital 0 nor 1. In general, metastability cannot be avoided, a problem that manifests whenever taking discrete measurements of analog values. Metastability of the output then reflects uncertainty as to whether a measurement should be rounded up or down to the next possible measurement outcome. Surprisingly, Lenzen and Medina (ASYNC 2016) showed that metastability can be contained, i.e., measurement values can be correctly sorted without resolving metastability first. However, both their work and the state of the art by Bund et al. (DATE 2017) leave open whether such a solution can be as small and fast as standard sorting networks. We show that this is indeed possible, by providing a circuit that sorts Gray code inputs (possibly containing a metastable bit) and has asymptotically optimal depth and size. Concretely, for 10-channel sorting networks and 16-bit wide inputs, we improve by 48.46% in delay and by 71.58% in area over Bund et al. Our simulations indicate that straightforward transistor-level optimization is likely to result in performance on par with standard (non-containing) solutions.
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