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arXiv 1801.04494cond-mat.mes-hall
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硅金属氧化物半导体量子点中前六个空穴的自旋填充和轨道结构

Spin filling and orbital structure of the first six holes in a silicon metal-oxide-semiconductor quantum dot

S. D. Liles, R. Li, C. H. Yang, F. E. Hudson, M. Veldhorst, A. S. Dzurak, A. R. Hamilton

摘要:

半导体量子点中电子的自旋态为量子计算提供了一个很有前途的平台。最近对硅CMOS量子位的研究表明,电子自旋态的相干操纵具有极高保真度。然而,单电子自旋的操纵需要在芯片上产生大的振荡磁场,使得当按比例放大到多量子位器件时难以寻址单个量子位。自旋-轨道相互作用使得自旋状态可以用电场控制,电场局部作用并且更容易产生。虽然硅中的电子的自旋-轨道相互作用较弱,但价带空穴具有固有的强自旋-轨道相互作用。然而,在一个适合放大到大量量子比特的架构中,创造一个可以定位单个空穴的硅量子点是一个挑战。在这里,我们报告了一个硅量子点,与集成的电荷传感器,可以操作到最后一个孔。我们绘制了前六个空穴的自旋态和轨道结构,并表明它们遵循Fock-Darwin谱。我们还发现,空穴-空穴相互作用是非常强的,减少了90%的单重态-三重态分裂相比,单粒子的水平间距为3.5毫电子伏。这些结果为在平面硅CMOS结构中实现单空穴自旋量子比特提供了一条途径。

英文摘要:

The spin states of electrons confined in semiconductor quantum dots form a promising platform for quantum computation. Recent studies of silicon CMOS qubits have shown coherent manipulation of electron spin states with extremely high fidelity. However, manipulation of single electron spins requires large oscillatory magnetic fields to be generated on-chip, making it difficult to address individual qubits when scaling up to multi-qubit devices. The spin-orbit interaction allows spin states to be controlled with electric fields, which act locally and are easier to generate. While the spin-orbit interaction is weak for electrons in silicon, valence band holes have an inherently strong spin-orbit interaction. However, creating silicon quantum dots in which a single hole can be localised, in an architecture that is suitable for scale-up to a large number of qubits, is a challenge. Here we report a silicon quantum dot, with an integrated charge sensor, that can be operated down to the last hole. We map the spin states and orbital structure of the first six holes, and show they follow the Fock-Darwin spectrum. We also find that hole-hole interactions are extremely strong, reducing the two-hole singlet-triplet splitting by 90% compared to the single particle level spacing of 3.5 meV. These results provide a route to single hole spin quantum bits in a planar silicon CMOS architecture.

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