具有静态处理器和存储器故障的PRAM的确定性计算
Deterministic Computations on a PRAM with Static Processor and Memory Faults
摘要：
本文研究了并行随机存取机（PRAM）中的部分处理器和存储单元发生故障的问题。所考虑的故障是静态的，即，一旦机器开始运行，PRAM组件的运行/故障状态不会改变。我们开发了一个确定性的模拟一个完全运作的PRAM在一个类似的故障机器，它有恒定的分数之间的处理器和存储单元的故障。模拟PRAM具有$n$处理器和$m$存储单元，并且模拟具有$n$处理器和恒定分数的$m$存储单元的PRAM。模拟分为两个阶段：首先是预处理，然后是以逐步方式正确执行的模拟。在时间$O((\frac{m}{n}+ \log n)\log n)$中执行预处理。模拟的逐步部分的减速是$O(\log m)$。
英文摘要：
We consider Parallel Random Access Machine (PRAM) which has some processors and memory cells faulty. The faults considered are static, i.e., once the machine starts to operate, the operational/faulty status of PRAM components does not change. We develop a deterministic simulation of a fully operational PRAM on a similar faulty machine which has constant fractions of faults among processors and memory cells. The simulating PRAM has $n$ processors and $m$ memory cells, and simulates a PRAM with $n$ processors and a constant fraction of $m$ memory cells. The simulation is in two phases: it starts with preprocessing, which is followed by the simulation proper performed in a step-by-step fashion. Preprocessing is performed in time $O((\frac{m}{n}+ \log n)\log n)$. The slowdown of a step-by-step part of the simulation is $O(\log m)$.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
