量子点元胞自动机中可配置时序电路的设计
Design of Configurable Sequential Circuits in Quantum-dot Cellular Automata
摘要：
量子点元胞自动机（QCA）是未来低功耗纳米级电子器件的可能候选者。QCA中的时序电路由于其在数字工业中的广泛应用而受到人们的广泛关注。另一方面，可配置器件提供低器件成本和器件面积的有效利用。由于任何时序逻辑电路的基本构件都是触发器，因此构造可配置的、多用途的QCA触发器是当前研究的主要重点之一。本文提出了一种可配置触发器（CFF）的设计方法，这是QCA领域中的第一个此类设计。通过配置触发器的控制输入，可以将其配置为D、T和JK触发器。此外，为了使触发器的可配置性更高，设计了一种时钟脉冲发生器（CPG），它可以触发时钟的所有类型的边缘（下降，上升和双）。在CPG的帮助下，使用相同的CFF设计来实现边缘可配置（双/上升/下降）触发器。使用边沿可配置（双/上升/下降）触发器的最大优点是，它可以使用相同的单个电路以9种不同的方式使用。所有提出的设计都使用QCADesigner仿真器进行了验证。
英文摘要：
Quantum-dot cellular automata (QCA) is a likely candidate for future low power nano-scale electronic devices. Sequential circuits in QCA attract more attention due to its numerous application in digital industry. On the other hand, configurable devices provide low device cost and efficient utilization of device area. Since the fundamental building block of any sequential logic circuit is flip flop, hence constructing configurable, multi-purpose QCA flip-flops are one of the prime importance of current research. This work proposes a design of configurable flip-flop (CFF) which is the first of its kind in QCA domain. The proposed flip-flop can be configured to D, T and JK flip-flop by configuring its control inputs. In addition, to make more efficient configurable flip-flop, a clock pulse generator (CPG) is designed which can trigger all types of edges (falling, rising and dual) of a clock. The same CFF design is used to realize an edge configurable (dual/rising/falling) flip- flop with the help of CPG. The biggest advantage of using edge configurable (dual/rising/falling) flip-flop is that it can be used in 9 different ways using the same single circuit. All the proposed designs are verified using QCADesigner simulator.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
