混合CPU上的分解组合优化--无CPU求解器结构
Combinatorial Optimization by Decomposition on Hybrid CPU--non-CPU Solver Architectures
摘要：
新的专用硬件（如FPGA或基于ASIC的退火机和量子处理器）的出现显示出比传统CPU更有效地解决某些复杂组合优化问题的潜力。我们表明，为了解决工业优化问题，CPU和非CPU设备的混合架构是不可避免的。在本文中，我们提出了一个有效的方法来设计一个混合的CPU-非CPU优化求解器的问题分解。我们介绍了所需的算法元素，使问题分解一个可行的方法，在满足现实世界的约束条件，如通信时间和潜在的更高的成本使用非CPU硬件。然后，我们转向著名的最大团问题，并提出了一个新的方法分解这个问题。我们的方法使我们能够解决非常大的图形上的最大团问题，使用非CPU的硬件，这是远远小于图形的大小。作为一个例子，我们证明了com-Amazon图上的最大团问题，有334，863个顶点和925，872条边，可以通过对一个设备的单次调用来解决，该设备可以嵌入一个大小至少为21个节点的全连接图，例如D-Wave 2000 Q。我们还表明，我们提出的问题分解方法可以提高两个最著名的经典算法的大型，稀疏图，即PMC和BBMCSP，数量级的运行时间。根据我们的研究，我们认为，如果能够大规模生产和高度并行化，或者能够为特定的小规模问题提供高质量的解决方案，那么新的非CPU硬件尺寸小，可以与CPU竞争。
英文摘要：
The advent of new special-purpose hardware such as FPGA or ASIC-based annealers and quantum processors has shown potential in solving certain families of complex combinatorial optimization problems more efficiently than conventional CPUs. We show that to address an industrial optimization problem, a hybrid architecture of CPUs and non-CPU devices is inevitable. In this paper, we propose problem decomposition as an effective method for designing a hybrid CPU--non-CPU optimization solver. We introduce the required algorithmic elements for making problem decomposition a viable approach in meeting the real-world constraints such as communication time and the potential higher cost of using non-CPU hardware. We then turn to the well-known maximum clique problem, and propose a new method of decomposition for this problem. Our method enables us to solve the maximum clique problem on very large graphs using non-CPU hardware that is considerably smaller than the size of the graph. As an example, we show that the maximum clique problem on the com-Amazon graph, with 334,863 vertices and 925,872 edges, can be solved with a single call to a device that can embed a fully connected graph of size at least 21 nodes, such as the D-Wave 2000Q. We also show that our proposed problem decomposition approach can improve the runtime of two of the best-known classical algorithms for large, sparse graphs, namely PMC and BBMCSP, by orders of magnitude. In the light of our study, we believe that new non-CPU hardware that is small in size could become competitive with CPUs if it could be either mass produced and highly parallelized, or able to provide high-quality solutions to specific, small-sized problems significantly faster than CPUs.
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