通过控制氢化Si（001）上的双原子台阶实现III-V/Si共集成
Toward III-V/Si co-integration by controlling biatomic steps on hydrogenated Si(001)
摘要：
III-V族在硅上的集成仍然是一个热门话题，因为它将开辟一条将硅CMOS逻辑与光子钳共同集成的途径。为了实现这一目标，应该解决几个障碍，更具体地说，在III-V/Si（001）界面处反相边界（APB）的产生。用密度泛函理论（DFT）证明了在适当的氢化学势下，名义Si（001）表面在退火过程中形成的双层台阶的存在.这种现象可以解释为形成的二聚体空位线，这可能是负责的优先和选择性蚀刻的一种类型的步骤，导致双台阶表面创建。为了验证这一假设，在工业300 mm MOCVD中进行了不同的实验，其中Si（001）表面退火步骤期间的总压力已经改变。在优化条件下，在标称Si（001）表面上生长了无APBs的GaAs层，为硅工业平台上的III-V集成铺平了道路。
英文摘要：
The integration of III-V on silicon is still a hot topic as it will open up a way to co-integrate Si CMOS logic with photonic vices. To reach this aim, several hurdles should be solved, and more particularly the generation of antiphase boundaries (APBs) at the III-V/Si(001) interface. Density functional theory (DFT) has been used to demonstrate the existence of a double-layer steps on nominal Si(001) which is formed during annealing under proper hydrogen chemical potential. This phenomenon could be explained by the formation of dimer vacancy lines which could be responsible for the preferential and selective etching of one type of step leading to the double step surface creation. To check this hypothesis, different experiments have been carried in an industrial 300 mm MOCVD where the total pressure during the anneal step of Si(001) surface has been varied. Under optimized conditions, an APBs-free GaAs layer was grown on a nominal Si(001) surface paving the way for III-V integration on silicon industrial platform.
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